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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hong Liu Ning Tang Mingliang Wang Zhao Xia Ke Zhang Tian Tong |
| Copyright Year | 2013 |
| Description | Author affiliation: 47th Res. Inst., China Electron. Technol. Group Corp., Shenyang, China (Ning Tang) || Shanghai Inst. of Microsyst. & Inf. Technol., Shanghai, China (Hong Liu; Mingliang Wang; Zhao Xia; Ke Zhang; Tian Tong) |
| Abstract | A 12-bit monolithic D/A converter has been developed. The principle of proportional match design in the resistor switch network, its structural characteristics and the resistor network for calibration are elaborated. In order to cancel the variation of switch network resistance value caused by process, temperature and voltage, a new calibration circuit has been proposed. Finally this paper proposed an automatic calibration algorithm based on fuse trim, which can significantly improve the efficiency of trimming and lower the cost of DAC chip. Simulation results show that the linear error, differential error and full scale error of the converter all meet the requirements of 12-bit resolution. Operating at 15V, the DAC achieves a settling time of 1us for full scale voltage. |
| Sponsorship | IEEE |
| Starting Page | 449 |
| Ending Page | 452 |
| File Size | 551564 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479924523 |
| DOI | 10.1109/ICECS.2013.6815451 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-12-08 |
| Publisher Place | United Arab Emirates |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Resistors Calibration Resistance Fuses Switches Accuracy Algorithm design and analysis |
| Content Type | Text |
| Resource Type | Article |
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