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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Manolopoulos, K. Reisis, D. Chouliaras, V.A. |
| Copyright Year | 2011 |
| Description | Author affiliation: Electronics Laboratory, Department of Physics, National and Kapodistrian University of Athens, Athens, Greece (Manolopoulos, K.; Reisis, D.) || Department of Electronic and Electrical Engineering, Loughborough University, Loughborough, LEICS, LE11 3TU, UK (Chouliaras, V.A.) |
| Abstract | The current paper presents a multi-mode floating point multiplier operating efficiently with every precision format specified by the IEEE 754–2008 standard. The design performs one quadruple precision multiplication, or two double precision multiplications in parallel, or four single precision multiplications in parallel. The proposed multiplier is pipelined to achieve execution of one quadruple multiplication in 3 cycles and either two double precision operations in parallel or four single precision operations in parallel in only 2 cycles. The proposed design improves the throughput by a factor of two compared to a double precision multiplier and by four compared to a single precision multiplication. An example implementation on VLSI verifies the design and it achieves a maximum operating frequency of 505 MHz. |
| Starting Page | 153 |
| Ending Page | 156 |
| File Size | 672213 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781457718458 |
| e-ISBN | 9781457718465 |
| e-ISBN | 9781457718441 |
| DOI | 10.1109/ICECS.2011.6122237 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-12-11 |
| Publisher Place | Lebanon |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Registers Computer architecture Throughput Physics Very large scale integration Adders Floating-point arithmetic |
| Content Type | Text |
| Resource Type | Article |
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