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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Marzaki, A. Bidal, V. Laffont, R. Rahajandraibe, W. Portal, J.-M. Bouchakour, R. |
| Copyright Year | 2011 |
| Description | Author affiliation: ST-Microelectronics, ZI de Rousset BP 2, F-13106 Rousset Cedex, France (Marzaki, A.; Bidal, V.) || IM2NP-UMR CNRS 6242 : Institut Matériaux et, Microélectronique Nanoscience de Provence, IMT Technopôle Château Gombert, F-13451 Marseille cedex 20, France (Laffont, R.; Rahajandraibe, W.; Portal, J.-M.; Bouchakour, R.) |
| Abstract | A new DCG-FGT (Dual-Control-Gate Floating-Gate Transistor) transistor model for static and transient simulations is presented. The PSP MOS description is used as a basis for the formulation of the conduction channel behavior. The floating gate potential is implicitly computed with an added charge neutrality relation that ensures a good convergence. The model is running under electrical simulator (ELDO) and is characterized thanks to ICCAP software. It has been validated on an advanced STMicroelectronics technology. The final objective of this work is to provide an accurate and scalable model available in design framework. |
| Starting Page | 228 |
| Ending Page | 231 |
| File Size | 1656216 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781457718458 |
| e-ISBN | 9781457718465 |
| e-ISBN | 9781457718441 |
| DOI | 10.1109/ICECS.2011.6122255 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-12-11 |
| Publisher Place | Lebanon |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Integrated circuit modeling Logic gates Transistors Mathematical model Electric potential Computational modeling Threshold voltage |
| Content Type | Text |
| Resource Type | Article |
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