NDLI: Performance gain from data and control dependency elimination in embedded processors

Content Provider	IEEE Xplore Digital Library
Author	Codreanu, V. Hobincu, R.
Copyright Year	2010
Description	Author affiliation: Faculty of Electronics, Telecommunications and Information Technology, University “Politehnica” of Bucharest, ETTI, Romania (Codreanu, V.; Hobincu, R.)
Abstract	This paper presents a way of increasing overall performance in embedded processors by introducing a multithreading interleaved execution model that can be applied to any Instruction Set Architecture. Usual acceleration techniques as superpipeline or branch prediction are not suited for embedded machines due to their inherent inefficiency. We will show that by removing dependencies within a processor and thus eliminating the need for extra hardware required for keeping the overall coherence, there will be a noticeable increase in performance (up to 450%) and also a decrease in size and power consumption. Also, this approach will maintain the backwards compatibility with the software legacy in order to keep the software changes to a minimum.
Starting Page	47
Ending Page	50
File Size	1410649
Page Count	4
File Format	PDF
ISBN	9781424484577
e-ISBN	9781424484607
DOI	10.1109/ISETC.2010.5679319
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-11
Publisher Place	Romania
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multithreading Processor Instruction sets Interleaved Pipelines Computer architecture Hazards Registers Embedded
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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