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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Matsumoto, S. Xing Zhou Jin Fukushima, T. Miyamura, M. Itatani, H. |
| Copyright Year | 2000 |
| Description | Author affiliation: P I R&D Co. Ltd, Yokohama, Japan (Matsumoto, S.) |
| Abstract | Meeting the challenging market-defined needs of CSPs requires a new substrate technology to provide higher I/O densities, higher performance, thinner and lighter packaging structures. In this paper, applications to CSP interposer (CSP-IP) processes of newly developed positive photosensitive block co-polyimides (PPI) are discussed. Block co-polyimides are prepared in organic polar solvents by a sequential addition co-polymerization process in the presence of a binary catalyst. PPI polymer solutions are derived from block co-polyimides including photo-sensitizers. Advantages of these PPIs include: (1) no imidization process needs at high temperature; (2) PPIs with strong adhesion to Cu, Al and Si wafers; (3) thinner polyimide films with high durability; (4) positive photo-patterns with high resolution; (5) PPIs with high T/sub g/. In CSP-IP packaging processes using PPI, PPI's UV resolution workability gives highly uniform 20 /spl mu/m diameter via holes and highly uniform solder bumps attached to the polyimide layers. As PPI requires no imidization process after drying and curing, the heat requirements of CSP-IP processes are under 200/spl deg/C, which enables additional layers of lead I/O patterning between solder bumps without any solder bump deformations, giving higher I/O densities and size reduction to the new CSP-IP. PPI's pin-holeless performance using black masks in the processes keeps CSP-IP production cost very low, and it is possible to coat PPI polymer solutions directly on Si wafers to produce a wafer CSP with high production yield at low cost. Thinner layered CSP-IP packages by PPI could be applied to 3D-stacked CSP features. |
| Starting Page | 367 |
| Ending Page | 372 |
| File Size | 795339 |
| Page Count | 6 |
| File Format | |
| ISBN | 0780366441 |
| DOI | 10.1109/EPTC.2000.906402 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2000-12-07 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Chip scale packaging Polyimides Production Costs Solvents Polymers Temperature Adhesives Semiconductor films Workability |
| Content Type | Text |
| Resource Type | Article |
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