NDLI: Addressing emerging test challenges for multilevel signaling devices

Content Provider	IEEE Xplore Digital Library
Author	Schroeder, G.
Copyright Year	2002
Description	Author affiliation: Credence Syst. Corp., Fremont, CA, USA (Schroeder, G.)
Abstract	Multilevel analog signaling techniques are rapidly gaining favor for their ability to provide very high-speed symbol transfer rates at appreciably lower observed line rates. Early bipolar methods such as Alternate Mark Inversion have paved the way to signaling techniques using four or more levels. In light of rapidly growing interest in multimedia communications, a particularly important application of multilevel signaling methods is Gigabit Ethernet (1000Base-T), which combines Five-level Pulse Amplitude Modulation (PAM5) with the use of parallel differential. signal lines to increase symbol rates while retaining low line rates. For device manufacturers, however, multilevel signaling poses new challenges for achieving reliable, high-throughput testing needed to deliver required levels of quality and production volume. Documented in IEEE Std 802.3ab-1999, the IEEE offers recommendations for several tests for 1000Base-T PHY devices to ensure signal integrity, timing and functional performance. Among these recommendations, specific test scenarios address the need for measurements of a range of amplitude, voltage, distortion, timing, jitter and functional characteristics. In turn, the measurement of these characteristics in multilevel signaling devices carries specific implications for signal generation and measurement. Very high frequency arbitrary waveform generators (AWGs) win be needed to address higher bandwidth signals across multiple independent differential channels used in applications such as Gigabit Ethernet. Similarly, integrated timing digitizers will be needed to complete time measurements including single-shot propagation delay (Tpd), jitter and frequency. By anticipating these and other emerging test challenges associated with multilevel signaling, device manufacturers will be able to avoid potential delays in production test and speed delivery of devices for this evolving market segment.
Starting Page	376
Ending Page	381
File Size	510172
Page Count	6
File Format	PDF
ISBN	0780373014
DOI	10.1109/IEMT.2002.1032782
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-07-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Distortion measurement Ethernet networks Manufacturing Production Timing jitter Signal generators Frequency Multimedia communication Pulse modulation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Addressing emerging test challenges for multilevel signaling devices.

High accuracy jitter measurement using cyclic pulse width modulation structure

Low-jitter transmission code for 4-PAM signaling in serial links

Modeling timing jitter effects in digital-to-analog converters

Synchronous phase-reset FM carrier recording for reference bursts

New simulation and test results for IEEE 802.1AS timing performance

Effects of amplitude modulation in jitter tolerance measurements of communication devices

Closed-loop Built in Self Test for PLL production testing with minimal tester resources

Tradeoffs between Timing Jitter and Mean-Time-to-Lose-Lock in DLL Code Tracking of CDMA Signals

Addressing emerging test challenges for multilevel signaling devices

Similar Documents

Addressing emerging test challenges for multilevel signaling devices.

High accuracy jitter measurement using cyclic pulse width modulation structure

Low-jitter transmission code for 4-PAM signaling in serial links

Modeling timing jitter effects in digital-to-analog converters

Synchronous phase-reset FM carrier recording for reference bursts

New simulation and test results for IEEE 802.1AS timing performance

Effects of amplitude modulation in jitter tolerance measurements of communication devices

Closed-loop Built in Self Test for PLL production testing with minimal tester resources

Tradeoffs between Timing Jitter and Mean-Time-to-Lose-Lock in DLL Code Tracking of CDMA Signals

Addressing emerging test challenges for multilevel signaling devices