NDLI: A novel borderless contact/interconnect technology using aluminum oxide etch stop for high performance SRAM and logic

Content Provider	IEEE Xplore Digital Library
Author	Subbanna, S. Harame, D. Chappell, B. Comfort, J. Davari, B. Franch, R. Danner, D. Acovic, A. Brodsky, S. Gilbreth, J. Robertson, D. Malinowski, J. Lii, T. Shahidi, G.
Copyright Year	1993
Description	Author affiliation: Semicond. Res. & Dev. Center, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA (Subbanna, S.; Harame, D.; Chappell, B.; Comfort, J.; Davari, B.; Franch, R.; Danner, D.; Acovic, A.; Brodsky, S.; Gilbreth, J.; Robertson, D.; Malinowski, J.; Lii, T.; Shahidi, G.)
Abstract	To keep pace with scaled technology and the requirements of SRAM for embedded high speed microprocessor cache, we use borderless contacts with an Al/sub 2/O/sub 3/ etch-stop and a combination of damascene and metal RIE local interconnect to achieve bulk 6T CMOS SRAM cell sizes from 34 to 15 /spl mu/m/sup 2/ (2-->4 Mb). The Al/sub 2/O/sub 3/ etch stop is RIE etched allowing the simultaneous formation of dense borderless contacts and low-resistance local interconnect, unlike previous approaches that wet etch the Al/sub 2/O/sub 3/. We have fabricated 64 K CMOS SRAMs with 5 ns access time suitable for 2 Mb embedded 2.5 V, 0.25 pm L/sub EFF/ SRAM technology using salicide, oxide planarization, dry etched Al/sub 2/O/sub 3/ etch stop, W damascene local interconnect layer, and two level AlCu metal. We have extended this technology to 4 Mb SRAM cells using a polycide gate stack damascene MO with contact to diffusion that is borderless to both gate and isolation edges, a second metal RIE local interconnect, and using a scaled device design.<>
Starting Page	441
Ending Page	444
File Size	364941
Page Count	4
File Format	PDF
ISBN	0780314506
ISSN	01631918
DOI	10.1109/IEDM.1993.347315
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-12-05
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Aluminum oxide Etching CMOS technology Random access memory Latches Isolation technology Planarization Integrated circuit interconnections Wiring Wire
Content Type	Text
Resource Type	Article
Subject	Materials Chemistry Electronic, Optical and Magnetic Materials Condensed Matter Physics Electrical and Electronic Engineering

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