NDLI: Projecting CMOS circuit hot-carrier reliability from DC device lifetime

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Projecting CMOS circuit hot-carrier reliability from DC device lifetime

Content Provider	IEEE Xplore Digital Library
Author	Quader, K.N. Ko, P.K. Chenming Hu
Copyright Year	1993
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA (Quader, K.N.; Ko, P.K.; Chenming Hu)
Abstract	We present generalized hot-carrier-reliability technology qualification and circuit design rules. The inverse duty factors, i.e. DC to AC time conversion factors for N- and P-MOSFETS are found to be 4/ft/sub rise/, and 10/ft/sub fall/ or 120 and 300 respectively. Typically, /spl Deltaspl tau/spl tau/ of an inverter is 1/4 /spl Delta/I/sub dI/sub d/ of NMOSFET minus 1/2 /spl Delta/I/sub dI/sub d/ of PMOSFET. The proposed design rules are valid for both 5 V and 3.3 V technologies and can be easily incorporated into existing DC lifetime prediction routines.<>
Starting Page	511
Ending Page	514
File Size	337202
Page Count	4
File Format	PDF
ISBN	0780314506
ISSN	01631918
DOI	10.1109/IEDM.1993.347299
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-12-05
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hot carriers MOSFET circuits Frequency Inverters Degradation Ring oscillators Stress Neodymium CMOS technology Qualifications
Content Type	Text
Resource Type	Article
Subject	Materials Chemistry Electronic, Optical and Magnetic Materials Condensed Matter Physics Electrical and Electronic Engineering

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