NDLI: A New Self-Aligned Nitride MTP Cell with 45nm CMOS Fully Compatible Process

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Plenary Session

Automotive Electronics - Enabling the future of individual mobility

Roles of Quantum Nanostructures on the Evolution and Future Advances of Electronic and Photonic Devices

Combining Digital Optical MEMS, CMOS and Algorithms for Unique Display Solutions

Integrated Circuits & Manufacturing - DRAM and Fuse Technology

Memory Technologies for sub-40nm Node

A novel cell arrangement enabling Trench DRAM scaling to 40nm and beyond

High performance Silicon-On-ONO (SOONO) Cell Array Transistors (SCATs) for 512Mb DRAM Cell Array Application

FBC's Potential of $6F^{2}$ Single Cell Operation in Multi-Gbit Memories Confirmed by a Newly Developed Method for Measuring Signal Sense Margin

A Novel Via-fuse Technology Featuring Highly Stable Blow Operation with Large On-off Ratio for 32nm Node and Beyond

CMOS Devices - Metal Gate & High-K Gate Dielectric

Low VT CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

Materials Science-based Device Performance Engineering for Metal Gate High-k CMOS

Flexible, simplified CMOS on Si(110) with metal gate / high k for HP and LSTP

Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2 gate stack

Intrinsic Origin of Electron Mobility Reduction in High-k MOSFETs - From Remote Phonon to Bottom Interface Dipole Scattering

Integration Technology of PC-FUSI (Phase Controlled FUSI) / HfSiON Gate Stack for Embedded Memory Application

Solid-State & Nanoelectronic Devices - SONOS and Charge Trapping Memory Devices

15 nm Planar Bulk SONOS-type Memory with Double Junction Tunnel Layers using Sub-threshold Slope Control

Trap Layer Engineered Gate-All-Around Vertically Stacked Twin Si -Nanowire Nonvolatile Memory

Novel ZrO2/Si3N4 Dual Charge Storage Layer to Form Step-Up Potential Wells for Highly Reliable Multi-Level Cell Application

A NAND-type Flash Memory Using Impact Ionization Generated Substrate Hot Electron Programming (≫20MB/sec) and Hot Hole Erasing

A New Self-Aligned Nitride MTP Cell with 45nm CMOS Fully Compatible Process

45nm Gateless Anti-Fuse Cell with CMOS Fully Compatible Process

Modeling & Simulation - Performance Analysis And Transport Modeling

Novel Carrier-Mobility Modeling with Interface States for MOSFETs with Highly Scaled Gate Oxide Based on First-Principles Calculations

On the experimental determination of channel back-scattering in nanoMOSFETs

Simulation of Electron Transport in High-Mobility MOSFETs: Density of States Bottleneck and Source Starvation

Performance Analysis of III-V Materials in a Double-Gate nano-MOSFET

On the Performance Limit of Impact-Ionization Transistors

Quantum Transport Simulation of Tunneling Based Spin Torque Transfer (STT) Devices: Design Trade offs and Torque Efficiency

Process Technology - Advanced Junctions, Silicides and Novel Stress Engineering

A New Liner Stressor with Very High Intrinsic Stress (≫ 6 GPa) and Low Permittivity Comprising Diamond-Like Carbon (DLC) for Strained P-Channel Transistors

Silicon-Germanium-Tin (SiGeSn) Source and Drain Stressors formed by Sn Implant and Laser Annealing for Strained Silicon-Germanium Channel P-MOSFETs

Interfacial Segregation of Metal at NiSi/Si Junction for Novel Dual Silicide Technology

A Novel Low Leakage-Current Ni SALICIDE Process in nMOSFETs on Si(110) Substrate

Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology

Low Temperature Implementation of Dopant-Segregated Band-edge Metallic S/D junctions in Thin-Body SOI p-MOSFETs

Pushing Planar Bulk CMOSFET Scaling to its Limit by Ultimately Shallow Diffusion-Less Junction

Extendibility of NiPt Silicide Contacts for CMOS Technology Demonstrated to the 22-nm Node

CMOS & Interconnect Reliability - Reliability Issues in Non-Volatile Memories and ESD

Reliability issues and scaling projections for phase change non volatile memories

Study of Local Trapping and STI Edge Effects on Charge-Trapping NAND Flash

First evidence for injection statistics accuracy limitations in NAND Flash constant-current Fowler-Nordheim programming

Random telegraph noise in flash memories - model and technology scaling

Characterization and Monte Carlo Analysis of Secondary Electrons Induced Program Disturb in a Buried Diffusion Bit-line SONOS Flash Memory

Modeling and Analysis of Self-Heating in FinFET Devices for Improved Circuit and EOS/ESD Performance

A Microscopic Understanding of Nanometer Scale DENMOS Failure Mechanism under ESD Conditions

Solid-State and Nanoelectronic Devices - Non- Classical Devices And Interconnects

A Perpendicular Spin Torque Switching based MRAM for the 28 nm Technology Node

Bended Gate-All-Around Nanowire MOSFET: a device with enhanced carrier mobility due to oxidation-induced tensile stress

Impact Ionization Nanowire Transistor with Multiple-Gates, Silicon-Germanium Impact Ionization Region, and Sub-5 mV/decade Subtheshold Swing

Pionics: the Emerging Science and Technology of Graphene-based Nanoelectronics

Fabrication and Characterization of Carbon Nanotube Interconnects

Carbon Nanotube Vias: A Reality Check

Displays, Sensors, and MEMS - Flexible And Organic Electronics

Matching Application-Specific Frontplanes With Generic Backplanes

An Approach to Cost-Effective, Robust, Large-Area Electronics using Monolithic Silicon

Communication sheets using printed organic nonvolatile memories

F-TES ADT Organic Integrated Circuits on Glass and Plastic Substrates

Label-free low-cost disposable DNA hybridization detection systems using organic TFTs

A 16-Byte Nonvolatile Bistable Polymer Memory Array on Plastic Substrates

Stackable Resistive Memory Device Using Photo Cross-linkable Copolymer

Integrated Circuits & Manufacturing - Advanced CMOS Logic and SoC Platforms

A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 $μm^{2}$ SRAM cell

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

Record RF performance of 45-nm SOI CMOS Technology

Technology Elements of a Common Platform Bulk Foundry Offering (Invited)

A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM

Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 $μm^{2}$ 6T-SRAM bitcell

CMOS Devices - High-Performance Devices

Novel Diffusion Topography Engineering (DTE) for High Performance CMOS Applications

Study on High Performance (110) PFETs with Embedded SiGe

High-Performance 45nm node CMOS Transistors Featuring Flash Lamp Annealing (FLA)

45nm High-k/Metal-Gate CMOS Technology for GPU/NPU Applications with Highest PFET Performance

High Performance Sub-40 nm Bulk CMOS with Dopant Confinement Layer (DCL) technique as a Strain Booster

Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates

(110) channel, SiON gate-dielectric PMOS with record high $I_{on}=1$ mA/μm through channel stress and source drain external resistance $(R_{ext})$ engineering

45nm SOI CMOS Technology with 3X hole mobility enhancement and Asymmetric transistor for high performance CPU application

Solid-State and Nanoelectronic Devices - Phase Change Memory and New Approaches for Nanoelectronics

Design Considerations for Complementary Nanoelectromechanical Logic Gates

Isotopically Engineered Silicon Nanoelectronics

Doped In-Ge-Te Phase Change Memory Featuring Stable Operation and Good Data Retention

Statistical analysis and modeling of programming and retention in PCM arrays

Evidence of the Thermo-Electric Thomson Effect and Influence on the Program Conditions and Cell Optimization in Phase-Change Memory Cells

A Novel Cross-Spacer Phase Change Memory with Ultra-Small Lithography Independent Contact Area

The Role of Interfaces in Damascene Phase-Change Memory

Process Technology - Gate Stack Process I - Fundamental Aspects

Tuning PMOS Mo(O,N) metal gates to NMOS by addition of DyO capping layer

Very Low Vt [Ir-Hf]/HfLaO CMOS Using Novel Self-Aligned Low Temperature Shallow Junctions

Mechanism of Vfb roll-off with High Work function Metal Gate and Low Temperature Oxygen Incorporation to Achieve PMOS Band Edge Work function

Comprehensive Study of VFB Shift in High-k CMOS - Dipole Formation, Fermi-level Pinning and Oxygen Vacancy Effect

Wide Controllability of Flatband Voltage by Tuning Crystalline Microstructures in Metal Gate Electrodes

Clarification of Additional Mobility Components associated with TaC and TiN Metal Gates in scaled HfSiON MOSFETs down to sub-1.0nm EOT

Impact of flash annealing on performance and reliability of high-κ/metal-gate MOSFETs for sub-45 nm CMOS

Emerging Technologies - Energy Harvesting Electron Devices

Developments in Silicon Solar Cells

Energy Harvesting - A Systems Perspective

Energy Harvesting for Electronics with Thermoelectric Devices using Nanoscale Materials

Nanogenerators and Nanopiezotronics

Micro-Engineered Devices for Motion Energy Harvesting

Quantum, Power, and Compound Semiconductors - Reliability and Characterization Of Power HEMTs

A review of failure modes and mechanisms of GaN-based HEMTs

Gate Current Degradation Mechanisms of GaN High Electron Mobility Transistors

Reliability of Enhancement-mode AlGaN/GaN HEMTs Fabricated by Fluorine Plasma Treatment

Drain Corrosion in RF Power GaAs PHEMTs

Remarkable Breakdown Voltage Enhancement in AlGaN Channel HEMTs

Characterisation of AlGaN/GaN HEMT epitaxy and devices on composite substrates

High-voltage Millimeter-Wave GaN HEMTs with 13.7 W/mm Power Density

Displays, Sensors, and MEMS - RF MEMS

Scalable 1.1 GHz fundamental mode piezo-resistive silicon MEMS resonator

Internal Dielectric Transduction of a 4.5 GHz Silicon Bar Resonator

Single-Resonator Dual-Frequency Thin-Film Piezoelectric-on-Substrate Oscillator

Integrated MEMS LC Resonator with Sealed Air-Suspended Structure for Single-Chip RF LSIs

Variable Capacitors and Tunable LC-Tanks Formed by CMOS-Compatible Metal MEMS for RF ICs

MEMS Variable Capacitor Actuated with an Electrically Floating Plate

High Reproducibility and Reliability of Piezoelectric MEMS Tunable Capacitors for Reconfigurable RF Front-end

Maneuvering Pull-in Voltage of an Electrostatic Micro-switch by Introducing a Pre-charged Electrode

Integrated Circuits & Manufacturing - Nonvolatile Memories

A High-performance Multi-level NAND Flash Memory with 43nm-node Floating-gate Technology

Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory

Thorough investigation of Si-nanocrystal memories with high-k interpoly dielectrics for sub-45nm node Flash NAND applications

Novel Ultra-Low Voltage and High-Speed Programming/Erasing Schemes for SONOS Flash Memory with Excellent Data Retention

Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory

CMOS Devices - Device/Design Interaction

Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies

Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS

Controllable Inverter Delay and Suppressing Vth Fluctuation Technology in Silicon on Thin BOX Featuring Dual Back-Gate Bias Architecture

Measurements of Inter-and-Intra Device Transient Thermal Transport on SOI FETs

An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits

Direct evaluation of DC characteristic variability in FinFET SRAM Cell for 32 nm node and beyond

CMOS & Interconnect Reliability - Advanced Dielectric Reliability

On the progressive breakdown statistical distribution and its voltage acceleration

Multiple Digital Breakdowns and Its Consequence on Ultrathin Gate Dielectrics Reliability Prediction

TDDB Reliability Prediction Based on the Statistical Analysis of Hard Breakdown Including Multiple Soft Breakdown and Wear-out

Multi-probe Two-Dimensional Mapping of Off-State Degradation in DeNMOS Transistors: How and Why Interface Damage Predicts Gate Dielectric Breakdown

Designing Reliable Systems with Unreliable Devices Challenges and Opportunities

Copper Wiring Encapsulation with Ultra-thin Barriers to Enhance Wiring and Dielectric Reliabilities for 32-nm Nodes and Beyond

Process Technology - Gate Stack Process II - Metal Gate / High K Integration

Feasible Integration Scheme for Dual Work Function FUSI/HfSiON Gate Stacks with Selective Metal Pile-up to nMOSFET

Gate-First Processed FUSI/HfO2/HfSiOx/Si MOSFETs with EOT=0.5 nm - Interfacial Layer Formation by Cycle-by-Cycle Deposition and Annealing

Single Metal/Dual High-k Gate Stack with Low Vth and Precise Gate Profile Control for Highly Manufacturable Aggressively Scaled CMISFETs

Practical dual-metal-gate dual-high-k CMOS integration technology for hp 32 nm LSTP utilizing process-friendly TiAlN metal gate

A Dy2O3-capped HfO2 Dielectric and TaCx-based Metals Enabling Low-Vt Single-Metal-Single-Dielectric Gate Stack

Band Edge Gate First HfSiON/Metal Gate n-MOSFETs using ALD-La2O3 Cap Layers Scalable to EOT=0.68 nm for hp 32 nm Bulk Devices with High Performance and Reliability

Aggressively Scaled High-k Gate Dielectric with Excellent Performance and High Temperature Stability for 32nm and Beyond

Modeling & Simulation - Development And Applications Of Compact Models For Advanced Circuit Design

A Unified Compact Model of the Gate Oxide Reliability for Complete Circuit Level Analysis

A predictive analytical model of 3D MIM capacitors for RC IC

Physically-based unified compact model for low-field carrier mobility in MOSFETs with different gate stacks and biaxial/uniaxial stress conditions

A new model for 1/f noise in high-κ MOSFETs

A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation

High Performance CMOS Variability in the 65nm Regime and Beyond

Rapid Circuit-based Optimization of Low Operational Power CMOS Devices

Displays, Sensors, and MEMS - TFTs, Displays and Memories

ZnO Thin Film Transistor Ring Oscillators with sub 75 nsec Propagation Delay

New Approach for Passivation of Ga2O3-In2O3-ZnO Thin Film Transistors

High performance transparent thin film transistors based on indium gallium zinc oxide as the channel material

Sub-Micron CMOS / MOS-Bipolar Hybrid TFTs for System Displays

New In-Situ Process of Top Gate Nanocrystalline Silicon Thin Film Transistors Fabricated at 180 °C for the Suppression of Leakage Current

Uniform High Current Field Emission of Electrons from Si and CNF FEAs Individually Controlled by Si Pillar Ungated FETs

Compact Nano-Electro-Mechanical Non-Volatile Memory (NEMory) for 3D Integration

Quantum, Power, and Compound Semiconductors - III-V FETs for Microwave, Millimiter Wave and Digital Applications

Sub 50 nm InP HEMT Device with Fmax Greater than 1 THz

610 GHz InAlAs/In0.75GaAs Metamorphic HEMTs with an Ultra-Short 15-nm-Gate

0.1 μm $In_{02}Al_{08}Sb-InAs$ HEMT low-noise amplifiers for ultralow-power applications

High Mobility III-V MOSFETs For RF and Digital Applications

Heterogeneous integration of enhancement mode $in_{0.7}ga_{0.3}as$ quantum well transistor on silicon substrate using thin (les 2 μm) composite buffer architecture for high-speed and low-voltage ( 0.5 v) logic applications

Logic Performance of 40 nm InAs HEMTs

90 nm Self-aligned Enhancement-mode InGaAs HEMT for Logic Applications

High performance submicron inversion-type enhancement-mode InGaAs MOSFETs with ALD Al2O3, HfO2 and HfAlO as gate dielectrics

Device/Circuit Interactions in Highly-Scaled CMOS: Challenges and Potential Solutions

Technology Circuit Co-Design for High Performance Logic

Variability Mitigation in Highly Scaled CMOS: Challenges for EDA

Leakage Reduction in Sub-100nm CMOS Technologies: Bridging the Gap Between Technology, Circuit Design and Low Power Product Requirements

An Adaptive Design of SRAM Memory Cell

Looking Beyond Silicon - A Pipe Dream or the Inevitable Next Step?

Quantum, Power, & Compound Semiconductors - Ultra High Speed SiGe and InP-based HBTs

SiGe BiCMOS Technology with 3.0 ps Gate Delay

A Novel Fully Self-Aligned SiGe:C HBT Architecture Featuring a Single-Step Epitaxial Collector-Base Process

Electrically pumped Ge Laser at room temperature

Type-II GaAsSb/InP DHBTs with Record fT = 670 GHz and Simultaneous fT, fMAX ≫ 400 GHz

600 GHz InP/GaAsSb/InP DHBTs Grown by MOCVD with a Ga(As,Sb) Graded-Base and $f_{T}$ x $BV_{CEO}$ ≫ 2.5 THz-V at Room Temperature

High-Speed InP HBT Technology for Advanced Mixed-signal and Digital Applications

Ferrite-Partially-Filled on-Chip RF Inductor Fabricated Using Low-Temperature Nano-Powder-Mixed-Photoresist Filling Technique for Standard CMOS

Process Technology - Advanced Process & Integration Technology

Embedded Flash on 90nm Logic Technology & Beyond for FPGAs

Gatestacks for scalable high-performance FinFETs

Route to Low Parasitic Resistance in MuGFETs with Silicon-Carbon Source/Drain: Integration of Novel Low Barrier Ni(M)Si:C Metal Silicides and Pulsed Laser Annealing

Si/SiGe Epitaxy: a Ubiquitous Process for Advanced Electronics

Localized SOI technology: an innovative Low Cost self-aligned process for Ultra Thin Si-film on thin BOX integration for Low Power applications

Proof of Ge-interfacing Concepts for Metal/High-k/Ge CMOS - Ge-intimate Material Selection and Interface Conscious Process Flow

CMOS Devices - Physics and Technologies of Mobility Enhancement

Extension of Universal Mobility Curve to Multi-Gate MOSFETs

More-than-Universal Mobility in Double-Gate SOI p-FETs with Sub-10-nm Body Thickness -Role of Light-Hole Band and Compatibility with Uniaxial Stress Engineering

Physical Understanding of Fundamental Properties of Si (110) pMOSFETs Inversion-Layer Capacitance, Mobility Universality, and Uniaxial Stress Effects

Mobility Enhancement in Uniaxially Strained (110) Oriented Ultra-Thin Body Single- and Double-Gate MOSFETs with SOI Thickness of Less Than 4 nm

Examination of Additive Mobility Enhancements for Uniaxial Stress Combined with Biaxially Strained Si, Biaxially Strained SiGe and Ge Channel MOSFETs

Interface-Engineered Ge (100) and (111), N- and P-FETs with High Mobility

High Performance pMOSFETs Using Si/Si1-xGex/Si Quantum Wells with High-k/Metal Gate Stacks and Additive Uniaxial Strain for 22 nm Technology Node

Modeling & Simulation - Nanotubes, Nanowires, and Nanoribbons

Three-dimensional Modeling of Gate Leakage in Si Nanowire Transistors

Band Structure Effects on the Current-Voltage Characteristics of SNW-FETs

1-D and 2-D Devices Performance Comparison Including Parasitic Gate Capacitance and Screening Effect

Exciton generation in suspended carbon nanotube FETs: a computational study

A Comprehensive Atomic Study of Carbon Nanotube Schottky Diode Using First Principles Approach

Analytical Model of Carbon Nanotube Electrostatics: Density of States, Effective Mass, Carrier Density, and Quantum Capacitance

Performance Comparison of Graphene Nanoribbon Schottky Barrier and MOS FETs

Simulation Investigation of Double-Gate CNR-MOSFETs with a Fully Self-Consistent NEGF and TB Method

Solid-State and Nanoelectronic Devices - Emerging Resistive RAM and New Function On Silicon

Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3 V

2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications

Conductive-filament switching analysis and self-accelerated thermal dissolution model for reset in NiO-based RRAM

Fast switching and long retention Fe-O ReRAM and its switching mechanism

A Novel Resistance Memory with High Scalability and Nanosecond Switching

A Silicon Photonics Approach for the Nanotechnology Era

Single-electron circuit for stochastic data processing using nano-MOSFETs

CMOS and Interconnect Reliability - Negative Bias Temperature Instability

New characterization and modeling approach for NBTI degradation from transistor to product level

Simultaneous Extraction of Recoverable and Permanent Components Contributing to Bias-Temperature Instability

Theory and Practice of On-the-fly and Ultra-fast VT Measurements for NBTI Degradation: Challenges and Opportunities

Material Dependence of NBTI Physical Mechanism in Silicon Oxynitride (SiON) p-MOSFETs: A Comprehensive Study by Ultra-Fast On-The-Fly (UF-OTF) IDLIN Technique

On-The-Fly Interface Trap Measurement and Its Impact on the Understanding of NBTI Mechanism for p-MOSFETs with SiON Gate Dielectric

Real Vth instability of pMOSFETs under practical operation conditions

New Observations on the Hot Carrier and NBTI Reliability of Silicon Nanowire Transistors

Impact of TiN Metal gate on NBTI assessed by interface states and fast transient effect characterization

Displays, Sensors, and MEMS - Chemical and Biological Sensors, and Microsystems

Three technologies for a smart miniaturized gas-sensor: SOI CMOS, micromachining, and CNTs - challenges and performance

AlGaN/GaN Heterostructure Field Effect Transistors for High Temperature Hydrogen Sensing with Enhanced Sensitivity

Improved Liquid Phase Chromatography Separation using Sub-micron Micromachining Technology

A Micro Ionizer for Portable Mass Spectrometers using Double-gated Isolated Vertically Aligned Carbon Nanofiber Arrays

Optoelectronic Tweezers for Manipulation of Cells and Nanowires

Integrated ZnO Surface Acoustic Wave Microfluidic and Biosensor System

Electrical measurement of adhesion and viability of living cells with a silicon chip

Quantum, Power, and Compound Semiconductors - High Voltage Power Devices

8300V Blocking Voltage AlGaN/GaN Power HFET with Thick Poly-AlN Passivation

650 V 3.1 $mΩcm^{2}$ GaN-based monolithic bidirectional switch using normally-off gate injection transistor

Current Collapseless High-Voltage GaN-HEMT and its 50-W Boost Converter Operation

High-performance p-channel diamond MOSFETs with alumina gate insulator

Stress-Induced Mobility Enhancement for Integrated Power Transistors

Impact of Self-Heating Effect on Hot Carrier Degradation in High-Voltage LDMOS

CMOS Devices - Advanced Device Structures

Observation of Mobility Enhancement in Strained Si and SiGe Tri-Gate MOSFETs with Multi-Nanowire Channels Trimmed by Hydrogen Thermal Etching

Investigation of nanowire size dependency on TSNWFET

New Self-Aligned Silicon Nanowire Transistors on Bulk Substrate Fabricated by Epi-Free Compatible CMOS Technology: Process Integration, Experimental Characterization of Carrier Transport and Low Frequency noise

Experimental Investigation on Superior PMOS Performance of Uniaxial Strained ≪110≫ Silicon Nanowire Channel By Embedded SiGe Source/Drain

A Novel Body Effect Reduction Technique to Recessed Channel Transistor Featuring Partially Insulating Layer Under Source and Drain : Application to Sub-50nm DRAM Cell

Ultra-Low Leakage Silicon-on-Insulator Technology for 65 nm Node and Beyond

High Performance 60 nm Gate Length Germanium p-MOSFETs with Ni Germanide Metal Source/Drain

Solid-State and Nanoelectronic Devices - Nanoscale Flash and DRAM Technologies

A High-Speed BE-SONOS NAND Flash Utilizing the Field-Enhancement Effect of FinFET

Highly Scalable Vertical Double Gate NOR Flash Memory

Advantages of the FinFET architecture in SONOS and Nanocrystal memory devices

New Generation of Z-RAM

A Unified-RAM (URAM) Cell for Multi-Functioning Capacitorless DRAM and NVM

Extremely Low-voltage and High-speed Operation Bulk Thyristor-SRAM/DRAM (BT-RAM) Cell with Triple Selective Epitaxy Layers (TEL)

Modeling and Simulation - Simulation of Processes and Advanced Memories

Physical interpretation, modeling and impact on phase change memory (PCM) reliability of resistance drift due to chalcogenide structural relaxation

Physical Model for NAND operation in SOI and Body-Tied Nanocrystal FinFLASH memories

Development of A 3D Simulator for Metal Nanocrystal (NC) Flash Memories under NAND Operation

Current Capabilities and Future Prospects of Atomistic Process Simulation

Analysis of As, P Diffusion and Defect Evolution during Sub-millisecond Non-melt Laser Annealing based on an Atomistic Kinetic Monte Carlo Approach

Experimental and Theoretical Analysis of Dopant Diffusion and C Evolution in High-C Si:C Epi Layers: Optimization of Si:C Source and Drain Formed by Post-Epi Implant and Activation Anneal

Novel doping technology for a 1nm NiSi/Si junction with dipoles comforting Schottky (DCS) barrier

Process Technology - Interconnect & 3D-IC's

32 nm node Ultralow-k(k=2.1)/Cu Damascene Multilevel Interconnect using High-Porosity (50 %) High-Modulus (9 GPa) Self-Assembled Porous Silica

Cost-effective and High Performance Cu Interconnects (keff=2.75) with Continuous SiOCH Stack Incorporating a Low-k Barrier Cap (k=3.1)

Bulk and interface band diagrams of advanced intermetal dielectrics

FR-4 and CMOS: Enabling Technologies for Consumer Volume Millimeterwave Applications

New Three-Dimensional Integration Technology Based on Reconfigured Wafer-on-Wafer Bonding Technique

Highly Reliable Thin MIM Capacitor on Metal (CoM) Structure with Vertical Scalability for Analog/RF Applications

Mass Production Worthy MIM Capacitor On Gate polysilicon(MIM-COG) Structure using HfO2/HfOxCyNz/HfO2 Dielectric for Analog/RF/Mixed Signal Application

Toward next high performances MIM generation: up to $30fF/μm^{2}$ with 3D architecture and high-κ materials

Displays, Sensors, and MEMS - Imagers and Optical Detectors

A 0.5 μm pixel frame-transfer CCD image sensor in 110 nm CMOS

Development of a Production-Ready, Back-Illuminated CMOS Image Sensor with Small Pixels

Two-Transistor Active Pixel Sensor for High Resolution Large Area Digital X-ray Imaging

Fully Implantable Retinal Prosthesis Chip with Photodetector and Stimulus Current Generator

3 D real-time CCD imager based on Background-Level-Subtraction scheme

Potentiality of Silicon Optical Modulator Based on Free-Carrier Absorption

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A New Self-Aligned Nitride MTP Cell with 45nm CMOS Fully Compatible Process

Content Provider	IEEE Xplore Digital Library
Author	Chia-En Huang Hsin-Ming Chen Han-Chao Lai Ying-Je Chen Ya-Chin King Chrong Jung Lin
Copyright Year	2007
Description	Author affiliation: Nat. Tsing-Hua Univ., Hsinchu (Chia-En Huang)
Abstract	A new 45 nm multiple time programming (MTP) cell with self-aligned nitride storage node has been proposed for logic NVM applications. The CMOS fully logic compatible cell has been successfully demonstrated in 45 nm CMOS technology with an ultra small cell size of 0.14 $mum^{2}.$ This cell adapting source side injection programming scheme has a wide on/off window and superior program efficiency. And it also exhibits excellent data retention capability even when logic gate oxide is less than 20 Aring with 45 nm gate length. This new cell provides a promising solution for logic NVM beyond 90 nm node.
Starting Page	91
Ending Page	94
File Size	3697255
Page Count	4
File Format	PDF
ISBN	9781424415076
DOI	10.1109/IEDM.2007.4418871
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS process Logic programming CMOS logic circuits Voltage CMOS technology Nonvolatile memory Industrial electronics Electronics industry Logic gates Space heating
Content Type	Text
Resource Type	Article

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5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in