NDLI: Fabrication of a 64K dynamic MOS RAM with tantalum silicide replacing polysilicon

Content Provider	IEEE Xplore Digital Library
Author	Yaney, D.S. Fogarty, T.N. Porter, R.A. Fraser, D.B. Murarka, S.P.
Copyright Year	1980
Description	Author affiliation: Bell Laboratories, Allentown, PA (Yaney, D.S.)
Abstract	Long polysilicon runners used for gates and interconnections in large devices limit performance due to RC delays encountered in propagating signals. As devices are scaled down for VLSI, thinner gates and field oxides as well as narrower runner widths tend to accentuate this problem. An order of magnitude decrease in sheet resistance with the corresponding improvement in RC delay is possible through the use of refractory metal silicides for these levels. In this work we describe the fabrication of a fully functional 64K NMOS dynamic RAM where TaSi2was substituted for polysilicon on the second poly level. We discuss the co-sputtering of the silicide on a poly "buffer" layer, annealing and subsequent plasma pattern definition. Final sheet resistance of the silicide level was under 3 ohms per square. In a related study, we have examined device I-V and MOS C-V characteristics and find no degradation due to these process changes. Together with the results of the physical fabrication, this work demonstrates the feasibility of this technology for extensive present and future application.
Starting Page	844
Ending Page	844
File Size	35261
Page Count	1
File Format	PDF
DOI	10.1109/IEDM.1980.189976
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1980-12-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fabrication Silicides Propagation delay Very large scale integration MOS devices DRAM chips Buffer layers Annealing Plasma properties Plasma devices
Content Type	Text
Resource Type	Article

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