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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kikkawa, T. Suganuma, T. Tanaka, K. Hara, T. |
| Copyright Year | 1980 |
| Description | Author affiliation: Nippon Electric Co., Ltd., Kawasaki City, Japan (Kikkawa, T.) |
| Abstract | A new complementary transistor structure has been developed. This paper presents a new technique which provides a fully complementary transistor structure for analog integrated circuits. The pnp transistor is fabricated by triple diffusion process in n type epitaxial layer on p type substrate, and is isolated from the substrate by inserting n- ion implanted layer between p+ collector buried layer and the substrate. This technique results in 5 to 10 times improvement in gain bandwidth product fT, maximum collector current IC(max)and collector saturation voltage VCE(sat)in comparison with conventional pnp transistors. Consequently, a fully complementary pnp transistor to npn transistors can be obtained. |
| Starting Page | 65 |
| Ending Page | 68 |
| File Size | 492996 |
| Page Count | 4 |
| File Format | |
| DOI | 10.1109/IEDM.1980.189754 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1980-12-08 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Analog integrated circuits Substrates Impurities Epitaxial layers Frequency Low voltage Ion implantation Diffusion processes Monolithic integrated circuits Fabrication |
| Content Type | Text |
| Resource Type | Article |
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