NDLI: A model for the parasitic SCR in bulk CMOS

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Front cover and table of contents

Plenary session—Invited papers

Resolution, overlay, and field-size for lithography systems

Semiconductor device development in the 1970s and 1980s—A perspective

Advances in bulk silicon and gallium arsenide materials technology

Session 2 Integrated circuits — Scaled devices

VHSIC Technology barriers

Experimental and theoretical characterization of submicron MOSFETs

An analytic charge-sharing predictor model for submicron MOSFETs

Optimization of self-aligned silicon MESFETs for VLSI at micron dimensions

Limiting factors for programming EPROM of reduced dimensions

Scaling the micron barrier with x-rays

Session 3 Device technology — Bipolar structures and technology

Polycrystalline devices in bipolar IC-technology

Application of polycrystalline silicon load for high performance bipolar memory

Application of low pressure silicon epitaxy to subnanosecond bipolar logic LSIS

A symmetrical bipolar structure

Scaling properties of bipolar devices

A new complementary transistor structure for analog integrated circuits

Session 4 Solid state devices — High power FETs

Monolithic MOS high voltage integrated circuits

Functional integration of power MOS and bipolar devices

A FET-controlled thyristor in SIPMOS technology

A new V.MOS/Bipolar Darlington transistor for power applications

High voltage, high current lateral devices

High frequency performance of VDMOS power transistors

2-D analysis of the negative resistance region of vertical power MOS-transistors

Session 5 Solid state devices — Microwave GaAs MESFETs

Quarter micron gate low noise GaAsFET's operable up to 30 GHz

High performance low noise FETs operating from X-band through Ka-band

A unique approach to Ku-band power FETs

Degradation of GaAs power MESFET's due to light emission

Thermal resistance of GaAs field-effect transistors

GaAs FET large signal model and design applications

A dual-gate MESFET for a high performance UHF TV tuner

Session 6 Device technology — Contacts and interconnects

Laser programmed vias for restructurable VLSI

A new self-aligned contact technology

A new MOS transistor design with self-registering source-drain and gate contacts

Stress-insensitive diffused resistor network for a high accuracy monolithic D/A converter

Planar plasma etching of Mo and MoSi2using NF3

Phosphorus doped molybdenum silicide technology for LSI applications

Aluminum patterning by ion implantation

Session 7 Electron tubes — Classical microwave tubes

Comparative status report on microwave sources

A high power millimeter wave TWT amplifier

Space tube with high efficiency cooling design approach

Average power limits of brazed-helix TWT's

Beam-beam interactions in concentric-beam dual-mode TWT's

Multimode injected-beam crossed-field amplifier for coherent airborne radar

A nonlinear theory for a microwave crossed field amplifier

A high power magnetron for air breakdown studies

Session 8 Quantum electronics and energy-conversion devices — Silicon solar cells

Recent developments in thermophotovoltaic conversion

Effects of design and process variations on silicon concentrator solar cell performance

A photovoltaic flux detector for the solar tower test facility

The physics of heavily-doped $n^{+}-p$ junction solar cells

Crystallographic structure effects on the electrical properties of polysilicon solar cells

Interface study of polycrystalline semiconductor-insulator-semiconductor (SIS) solar cells: Indium tin oxide on polysilicon

Impediment of the majority carrier current by grain boundary potential in Al-poly-Si Schottky barrier solar cells

Session 9 Device technology — Process modeling and characterization

Simulating VLSI wafer topography

Process modeling of multilayer structures involving polycrystalline silicon

Process design using coupled 2D process and device simulators

Two-dimensional integrated circuit process modeling program - RECIPE

Improvements in method and apparatus for determining minority carrier diffusion length

Capacitance measurement technique in high density MOS structures

Raman spectroscopy for evaluating laser annealed silicon layers

Session 10 Integrated circuits—CMOS technologies

Comparison of bulk silicon and SOS for VLSI CMOS

Elimination of latch up in bulk CMOS

A model for the parasitic SCR in bulk CMOS

SOS/CMOS as a high performance LSI device

Parasitic capacitance influence in micron and submicron CMOS/SOS

A high voltage-high frequency SOS/CMOS pulse generator

Session 11 Solid state devices—Junction device phenomena

Measurements of band gap narrowing in heavily doped epitaxial emitters and the modeling of heavily doped silicon

Verification of heavy doping parameters in semiconductor device modeling

A minority-carrier transport model for polysilicon contacts to silicon bipolar devices, including solar cells

Low temperature recombination lifetime in Si MOSFET's

A model for turn-off in bipolar transistors

A new model for the second breakdown of bipolar transistors

An experimental study of reverse-bias second breakdown

Session 12 Electron tubes—Fast wave devices

200 kW pulsed and CW gyrotrons at 28 GHz

A high power gyrotron operating in a high order mode

A C-band gyro-TWT

A high gain single stage gyrotron traveling-wave amplifier

Circuitless electron beam amplifier (CEBA)

A small signal theory of the peniotron

High gain deflection modulated microwave amplifiers using electric deflection

Session 13 Detectors, sensors and displays—Detector arrays

Monolithic InSb CID staring array

Performance of hybrid silicon focal planes

Hybrid focal plane arrays for infrared imaging devices

Low dark current glass bonded AlGaAs/GaAs Schottky gate imaging CCD

An interline-transfer CCD imager with floating photodiodes

An interline transfer CCD for a single sensor 2/3" color camera

Non-destructive image sensor

Session 14 Quantum electronics and energy conversion devices—Lasers and light emitting diodes

(AlGa)As DH lasers grown by molecular beam epitaxy for optical communication systems

Low-threshold high-T0constricted double heterojunction AlGaAs lasers

High-power leaky mode multiple-stripe laser

Transverse modal behavior of transverse junction stripe laser excited by short electrical pulse

Electrical-optical characteristics of buried waveguide heterostructure InGaAsP injection lasers

Effects of Auger recombination on double heterojunction 1.3 µm GaInAsP/InP light-emitting diodes

Optical and electrical characteristics of pulsating 1.3 µm InGaAsP double heterostructure lasers

Session 15 Integrated circuits—Bipolar integrated circuits

High frequency bipolar - JFET - $I^{2}L$ process

Multi-collector ECL circuit family and its application to 1 GHz prescaler IC

Propagation delay time dependence on gate geometry for the self-aligned $I^{2}L$

A bipolar transistor model of quasi-saturation for use in computer aided design (CAD)

GaAs bipolar integrated circuit technology

Session 16 Device technology—Pattern definition

Reactive ion etching for VLSI

Dry etching technology for 1 µm VLSI fabrication

Etch uniformity in a CCl4plasma aluminum etch

A high resolution double layer photoresist structure for lift-off technology

Status of x-ray lithography

Evaporated AgBr as an x-ray sensitive layer in a two-layer resist system for x-ray lithography

Electron-beam direct writing technology for 1 µm VLSI fabrication

A 1 µm process: Linewidth control using 10:1 projection lithography

Session 17 Solid state devices—Compound semiconductor device technology

Double heterojunction GaInAs devices by MBE

Advanced processing techniques for GaAs monolithic integrated circuits

GaAs IGFET: A new device for high speed digital ICs

Fabrication and performance of InP MISFET

InP millimeter wave Schottky barrier mixer diodes for low local oscillator power requirements

Fabrication and evaluation of GaAs-GaAlAs double-velocity IMPATT diodes

GaAs planar doped barriers by molecular beam epitaxy

Session 18 Electron tubes—Tube technology

Review of field emitter array cathodes

A study of thermionic emitters in the regime of practical operation

The M-type cathode — No longer magic?

Integrated grid technology

Three dimensional simulation of gridded TWT guns

Thermal and mechanical effects on gyrotron gun anode electrical performance

Experimental evaluation of PPM focussed electron beams

Session 19 Detectors, sensors and displays—Detector physics

LWIR HgCdTe photovoltaic detectors for hybrid focal plane arrays

HgCdTe photodiode mosaics on vapor phase epitaxial layers

Current mechanisms and 1/f noise in 8-12 µm $n^{+}on$ p (Hg,Cd)Te photodiodes

Thermal diffusion current mechanisms in $n^{+}-p-p^{+}Hg1-xCdxTe$ photodiodes

Dark current limitations in p-type Hg1-xCdxTe MIS devices

Space charge spectroscopy in Hg1-xCdxTe $n^{+}-p$ photodiodes

Increased charge capacity in Hg1-xCdxTe MIS devices using a ramped gate voltage

Characteristics of high value polysilicon resistors for use in IR hybrid focal plane arrays

Session 20 Quantum electronics and energy conversion devices — Optical devices

InP/InGaAs heterojunction bipolar phototransistors with improved sensitivity

High performance 1.3 µm InGaAsP edge-emitting LEDs

Recent advances in high efficiency, low-cost GaAs solar cells

The role of interface states in photoelectrochemical cells

Experimental and theoretical studies of high efficiency a-Si:F:H MIS solar cells

Current collection mechanisms in p-n junction a-Si:H solar cells using spectral response analysis

Session 21 Microstructure issues in the 80's

Session 22 Device technology — Advanced process and device concepts

Laser-recrystallized silicon-on-oxide—The ideal silicon-on-insulator structure for VLSI?

MOSFETs Fabricated in {100} single crystal silicon-on-oxide obtained by a laser-induced lateral seeding technique

Properties of thin oxynitride gate dielectrics produced by thermal nitridation of silicon dioxide

Selective polysilicon oxidation technology for defect free isolation

The influence of temperature on the tolerances of MOS-transistors in a 1 µm technology

Plasma resist image stabilization technique (PRIST)

Session 23 Integrated circuits — MOS memory technology

Soft error improvement of dynamic RAM with Hi-C structure

A new dynamic RAM cell for VLSI memories

A high speed 2k × 8 bit NMOS static RAM with a new double poly-Si gate memory cell process

Electrically alterable read-only memory cell with graded energy band-gap insulator

A 50 ns/15 V alterable n-channel nonvolatile memory device

Electrically alterable programmable logic array (EAPLA)

Triple level polysilicon $E^{2}PROM$ with single transistor per bit

Session 24 Solid state devices — Permeable base transistors and ballistic devices

Recent experimental results on permeable base transistors

Ballistic transport in semiconductor devices

Ballistic and collision dominated transport in a short semiconductor diode

Transverse magnetoresistance in GaAs two terminal submicron devices: A characterization of electron transport in the near ballistic regime

Velocity overshoot investigations in sub-micron GaAs devices by photoconduction experiments

Tunneling hot electron transfer amplifiers (THETA): A proposal for novel amplifiers operating in the subpicosecond range

Ballistic electron impact ionization in GaAs and in InP avalanche devices

Session 25 Solid state devices — New thyristor development

Light activated triacs and high voltage thyristors

A 6000 V, 1500 A light activated thyristor

Totally light controlled switch and new means for electrical turn-off of thyristors

Investigations of gate turn-off structures

High temperature performance of field controlled thyristors

Effects of gate structure on static induction thyristor

High power subnanosecond switch

Session 26 Detectors, sensors and displays — Sensors

The evolution from components to integrated optoelectronics circuits

A new silicon micro-transducer for the measurement of the magnitude and direction of a magnetic-field vector

Micromechanical accelerometer integrated with MOS detection circuitry

A monolithic thermopile detector fabricated using integrated-circuit technology

Pyroelectric anemometers

An MOS chip for surface impedance measurement and moisture monitoring

Electrolyte-insulator-semiconductor field-effect transistor

Steering of high frequency low level photocurrents between summing busses beyond the gm/2πC limit

Session 27 Detectors, sensors and displays — Displays

Matrix addressing flat-panel displays

Polysilicon FET devices for large area input/output applications

A 68 line multiplexed liquid crystal display using metal-insulator-metal (MIM) devices

A storage CRT using a thin-film electroluminescent screen

Thin film AC ZnSxSe1-x:Mn EL

Multi-color thin film emitters

Session 28 Integrated circuits — Device models

Interaction of IGFET field design with narrow channel device operation

Two dimensional nature of diffused line capacitance in coplanar MOS structures

Modeling and VLSI design constraints of substrate current

Characterization of two step impact ionization and its influence in NMOS and PMOS VLSI's

Small width effects on MOSFET hot-electron reliability

Threshold voltage instability in MOSFET's due to channel hot hole emission

Session 29 Device technology — IGFET technology

Twin-tub CMOS - A technology for VLSI circuits

A high speed buried channel MOSFET isolated by an implanted silicon dioxide layer

VLSI—A totally self-aligned MOS transistor

New edge-defined vertical-etch approaches for submicrometer MOSFET fabrication

Fabrication and characterization of e-beam defined MOSFETs with sub-micrometer gate lengths

Electron beam lithography for small MOSFETs

A 22ns 4K-bit SRAM fabricated with direct electron beam lithography

Session 30 Solid state devices — Novel devices and materials

Progress in conducting polymers: Studies of polyacetylene

Recessed gate junction field effect transistors

Subsurface junction field effect transistor (SJFET)

The junction MOS (JMOS) transistor - A high speed transistor for VLSI

Basic properties of lateral MIS tunnel transistor

Weakly inverted MOSFETs and their applications

A novel amorphous-silicon inverter circuit

Average power limits of brazed-helix TWT's

A small signal theory of the peniotron

Experimental evaluation of PPM focussed electron beams

Self-aligned npn bipolar transistors

A microwave silicon power MOSFET

Planar, ion-implanted GaAs bipolar transistors

Refractory metal silicide/N+ polysilicon in CMOS/SOS

A surface kinetics model for plasma etching

A new conduction model for polycrystalline silicon films

An N-well C-MOS dynamic RAM

A sub-nanosecond ISL technology demonstrated in a 400 mil × 400 mil VLSI chip

The influence of bandgap narrowing and impurity deionization on the characteristics of silicon bipolar microwave transistors

Low cost high burnout millimeter GaAs Schottky barrier flip chip diodes

Monolithic integration of widegap GaAlAs/GaAs phototransistors and LEDs as amplifying wavelength converters and photothyristors

The integrated optic spectrum analyzer - A first demonstration

Fabrication of a 64K dynamic MOS RAM with tantalum silicide replacing polysilicon

Lateral epitaxy by seeded solidification for growth of single-crystal Si films on insulators

Threshold behaviour of conductivity in polycrystalline semiconductor thin film transistors

A planar-processed PI-FET accelerometer

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A model for the parasitic SCR in bulk CMOS

Content Provider	IEEE Xplore Digital Library
Author	Raburn, W.D.
Copyright Year	1980
Description	Author affiliation: Harris Semiconductor, Melbourne, Florida (Raburn, W.D.)
Abstract	A model is presented for the parasitic SCR in bulk CMOS. The model shows the exact way that the shunting resistances alter the terminal V-I characteristics. It describes a negative differential resistance (NDR) range which is the only requirement for latch-up if certain biasing conditions are met. The NDR region will start when the product of current and shunting resistance equals the built in voltage and will occur for an+ ap< 1 (or βnβp< 1). The conditions for the center junction to become forward biased are given. If these conditions are met, the SCR will latch-up. If these conditions are not met, latch-up becomes dependent on the biasing circuit.
Starting Page	252
Ending Page	255
File Size	420365
Page Count	4
File Format	PDF
DOI	10.1109/IEDM.1980.189807
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1980-12-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling Thyristors Equations Semiconductor process modeling Voltage Circuits Gold Doping Neutrons Ionization
Content Type	Text
Resource Type	Article

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