NDLI: Soft error improvement of dynamic RAM with Hi-C structure

Content Provider	IEEE Xplore Digital Library
Author	Yamada, M. Taniguchi, M. Yoshihara, T. Takano, S. Matsumoto, H. Nishimura, T. Nakano, T. Gamou, Y.
Copyright Year	1980
Description	Author affiliation: Mitsubishi Electric Corporation, Hyogo, Japan (Yamada, M.)
Abstract	A novel Hi-C RAM cell is proposed for reducing the alpha-particle-induced soft error rate. The novel cell utilizes the doubly-implanted Hi-C struture combined with the boosted storage gate, which provides much alignment tolerance to the implantation steps for the Hi-C cell. This Hi-C cell having a charge storage capacity 30% larger than that of the conventional cell results in one order of magnitude decrease in soft errors as compared with the conventional one. The concept of this excellent cell is successfully demonstrated by a 64K dynamic RAM fabricated on the basis of a 3 pm design rule. Experimental results on refresh time of the 64K dynamic RAM indicates that the Hi-C cell has been realized without defective effects on the leakage of the stored charge.
Starting Page	578
Ending Page	581
File Size	523446
Page Count	4
File Format	PDF
DOI	10.1109/IEDM.1980.189899
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1980-12-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	DRAM chips Error analysis Read-write memory Substrates Random access memory Boron Testing Implants Leakage current Electrons
Content Type	Text
Resource Type	Article

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