NDLI: 300 mm process integration for 0.13 /spl mu/m generation with Cu/low-k interconnect technology

Content Provider	IEEE Xplore Digital Library
Author	Chang, W. Chen, C.C. Lu, J.C. Liou, S.J. Tsai, W.J. Liu, S.Y. Lee, H.J. Wang, Y.I. Lin, H.C. Yeh, C.H. Linliu, K. Chang, S.Z. Shen, S.J. Chen, L.W. Peng, S.S. Hung, S.H. Hsiao, Y.L. Hsieh, C.N. Li, C.I. Chang, M. Lee, K.H.
Copyright Year	2001
Description	Author affiliation: Taiwan Semicond. Manuf. Co., Tainan, Taiwan (Chang, W.)
Abstract	Successfully transferring to a 300 mm process from a leading-edge 200 mm 0.13 /spl mu/m CMOS technology using 248 nm lithography and Cu/low-k interconnect is demonstrated in the TSMC 300 mm Pilot Line. To achieve good performance with decent throughput, a 1 to 2.5 scaling factor for process power and gas flow is applicable for CVD and dry etch. Good within wafer (WIW) gap-fill for STI and ILD is obtained. WIW thin oxide non-uniformity is less than +/-1.6% by introducing O/sub 2/ gas at the ramp down stage. An OPC model set up for the 200 mm process can be used directly in the 300 mm process with comparable WIW CD uniformity. With good poly CD uniformity from proper etch process tuning, acceptable line end shortening control for 0.10 /spl mu/m devices is shown. In Cu/low-k interconnect, good patterning integrity is achieved with no edge delamination after Cu CMP. A good yield of 880 k via chain with tight multi-level Rs and low leakage is obtained. An excellent yield of 4 metal levels 4M SRAM that is comparable to 200 mm is also achieved by this 300 mm process.
Sponsorship	Electron Devices Soc. IEEE
File Size	380787
File Format	PDF
ISBN	0780370503
DOI	10.1109/IEDM.2001.979577
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-12-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Lithography Throughput Fluid flow Semiconductor device modeling Semiconductor device manufacture Manufacturing industries CMOS process Dry etching Delamination
Content Type	Text
Resource Type	Article

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