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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Isobe, K. Kanda, M. Murakami, T. Totsuka, K. Moriuchi, M. Miyoshi, T. Yamada, S. Noguchi, T. |
| Copyright Year | 2001 |
| Description | Author affiliation: Syst. LSI Div., Toshiba Corp., Yokohama, Japan (Isobe, K.) |
| Abstract | Flash memory cell characteristics degradation modes induced by copper (Cu) contamination have been investigated in detail. In addition, process integration for embedded flash memory within logic devices using Cu interconnection has been established. Due to Cu contamination, after stress induced by channel hot electron injection, interface-states located at the drain overlap region are accelerated. This leads to degradation of programmed cell threshold voltage (Vt) lowering. After Fowler-Nordheim (F-N) current stress, generation of electron trap sites in tunnel oxide is enhanced by the Cu, resulting in degradation of gate stress characteristics and data retention characteristics. However, with F-N stress, the increment of the number of trapped electrons in the tunnel oxide is not severe for embedded NOR flash applications used within up to 10/sup 4/ write/erase (W/E) cycles. As a result, the erased cell Vt rise is almost the same as that of a reference sample. |
| Sponsorship | Electron Devices Soc. IEEE |
| File Size | 319054 |
| File Format | |
| ISBN | 0780370503 |
| DOI | 10.1109/IEDM.2001.979612 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-12-02 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Contamination Degradation Copper Stress Electron traps Flash memory cells Flash memory Logic devices Channel hot electron injection Acceleration |
| Content Type | Text |
| Resource Type | Article |
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