NDLI: Power and Ground Bounce Effects on Component Performance Based on Printed Circuit Board Edge Termination Methodologies

Content Provider	IEEE Xplore Digital Library
Author	Montrose, M.I. Liu En-Xiao
Copyright Year	2007
Description	Author affiliation: Montrose Compliance Services Inc., Santa Clara (Montrose, M.I.)
Abstract	Printed circuit boards (PCBs) are one source of radiated EMI with digital components the culprits. To minimize development of common-mode currents within the silicon package of large current consuming circuits, a stable power distribution network (PDN) is required. Any noise (bounce) on either the power or 0 V reference (ground) plane may cause simultaneously switching noise (SSN) or signal integrity (SI) problems, as well as EMI. In addition, if planar bounce exceeds margin levels, components may not function. To ensure a stable PDN is present, decoupling capacitors and buried capacitive structures are mandatory, along with minimizing loop inductance. The uniqueness of this research lies in analyzing planar bounce that may exceed voltage margin levels from reflected EM waves that propagate back to components from the physical edge of the PCB. The edges of a PCB are in reality a high-impedance, non- terminated signal transmission line stub. With each reflection, ringing occurs. The magnitude of this ringing may cause digital components to have SSN and/or EMI problems. Popular board edge termination techniques are invested to determine if a designer should be concerned with reflected wave switching noise on either a power or 0 V reference plane, which cannot be removed by capacitive structures or decoupling.
Starting Page	1
Ending Page	6
File Size	418067
Page Count	6
File Format	PDF
ISBN	1424413494
DOI	10.1109/ISEMC.2007.114
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-07-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Printed circuits Electromagnetic interference Circuit noise Silicon Packaging Power systems Capacitors Inductance Voltage Power transmission lines
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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