NDLI: Accurate System Voltage and Timing Margin Simulation in CDR Based High Speed Designs

Content Provider	IEEE Xplore Digital Library
Author	Lambrecht, F. Qi Lin Sam Chang Dan Oh Chuck Yuan Stojanovic, V.
Copyright Year	2006
Description	Author affiliation: Rambus Inc., Los Altos, CA (Lambrecht, F.; Qi Lin; Sam Chang; Dan Oh; Chuck Yuan; Stojanovic, V.)
Abstract	Accurate analysis of system timing and voltage margin at a target bit error rate across process, voltage, and temperature variations is required for high volume production of high speed systems. This in turn requires a statistical simulation framework to model the effectiveness of advanced signaling techniques such as transmitter equalization and receiver decision feedback. Furthermore, for data and telecommunication networking serial links, one must also carefully model the clock-data recovery circuits (CDR) and understand their impact on system voltage and timing margin. In this paper, we first present a stochastic simulation framework and describe a modeling methodology for CDR circuits. We then compare the simulation results based on CDR modeling to a simple method, which uses a quadrature sampling based timing recovery model. Finally, we correlate the simulation results to lab measurements to validate the proposed approach
Sponsorship	IEEE Microwave Theory and Techniques Soc. IEEE Components, Packaging and Manuf. Techol. Soc
Starting Page	171
Ending Page	174
File Size	3916623
Page Count	4
File Format	PDF
ISBN	1424406684
DOI	10.1109/EPEP.2006.321220
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage Timing Circuit simulation Bit error rate Temperature Production systems Transmitters Decision feedback equalizers Clocks Stochastic processes
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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