NDLI: Roughness characterization of gate all around Silicon Nano Wire fabrication

Content Provider	IEEE Xplore Digital Library
Author	Levi, S. Schwarzband, I. Kris, R. Adan, O.
Copyright Year	2012
Description	Author affiliation: Applied Materials Israel, Rehovot, Israel (Levi, S.; Schwarzband, I.; Kris, R.; Adan, O.)
Abstract	In this paper we present a new methodology to calibrate and correct in line roughness measurements for Silicon Nano Wires (SiNW) fabrication processes. For successful implementation of these processes in industry, the Silicon Nano Wires (SiNW) with widths of 5–25 nm should be characterized in the framework of Secondary Electron Microscope(CD SEM) Metrology. Different smoothing processes yield SiNWs with edge roughness values in the sub nanometer range[1]. Such small differences in roughness values provide an interesting opportunity to evaluate sensitivity of the SEM metrology algorithms and measurement accuracy. A simulation program modeling SEM images including small features was developed, taking into account the main factors that affect the SEM signal formation. Synthetic (simulated) images of SiNW in a range of 5–25 nm and roughness of 0–1 nm were produced. Using synthetic images with added Line Edge Roughness (LER), we characterized the performance and sensitivity of LER algorithms and CD metrics.
Starting Page	1
Ending Page	5
File Size	703256
Page Count	5
File Format	PDF
ISBN	9781467346825
e-ISBN	9781467346818
DOI	10.1109/EEEI.2012.6376991
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-14
Publisher Place	Israel
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Numerical analysis Scanning electron microscopy Noise Mathematical model Wires Metrology Accuracy SEM Simulation CD SEM Metrology Roughness Nanowires
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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