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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hadj Abderrahmane, L. Bacha, M. Mebrek, A. |
| Copyright Year | 2014 |
| Description | Author affiliation: Centre of Satellite Dev. (CDS), Algerian Space Agency (ASAL), Arzew-Oran, Algeria (Hadj Abderrahmane, L.; Bacha, M.; Mebrek, A.) |
| Abstract | The interleaver represents an important part in the Turbo coding performance improvement. Moreover, the increase in the interleaver size generates good performances for Turbo code. The major technical contribution of this work is the new interleaver design using chaotic sequences to produce the dither in the golden interleavers. The new interleaver is proposed to carry out powerful interleavers correcting the bursts errors effectively. Simulation results are detailed in terms of the optimal solution observed along with the estimated BER and FER versus Eb/N0. For the simulated cases of the interleavers, good performance is obtained with the chaotic golden interleaver (CI) when transmitting data both in short block lengths (N=400 bits), and long block lengths (N=1024). The resulting curves are compared to more popular interleaver structures, namely dithered golden interleaver (DGI interleaver) to demonstrate the chaotic sequence ability to improve the turbo code performance. |
| Starting Page | 1 |
| Ending Page | 5 |
| File Size | 525924 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781479930999 |
| ISSN | 08407789 |
| e-ISBN | 9781479931019 |
| DOI | 10.1109/CCECE.2014.6900945 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-05-04 |
| Publisher Place | Canada |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Chaotic communication Bit error rate Turbo codes Correlation AWGN channels Vectors performance chaos golden interleaver turbocode |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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