NDLI: Heuristic method in searching for global minima relative to high voltage ac error

Content Provider	IEEE Xplore Digital Library
Author	Han, L. Peters, J.F.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada (Han, L.; Peters, J.F.)
Abstract	Searching for global minima is difficult and is still considered an unsolved problem in the study of optimization algorithms. In this paper, a heuristic method for searching for global minima relative to high voltage (HV) AC error is discussed. This heuristic method is important in the design of a HV power fault classification system such as the one described by L. Han et al. (1999). In this system signals, AC voltage error and 6 pulse signals etc., are preprocessed in feature information needed to calibrate a neural network for fault type classification. The feature information is ranged into low, medium or high distributions. Each partition should be optimized according to a criterion, namely, forcing the data points from the same type of fault to fall into the same range. Based on the AC error signals and associated fault-type, a 2-dimensional optimization problem with inequality constraints can be set up. To optimize the partition, we apply the new global minimum/maximum search algorithm. The comparison with the traditional bracketed interval method is discussed and this new method's simulation result is provided.
Sponsorship	Dept. Electr. & Comput. Eng. Faculty of Graduate Studies Faculty of Eng. TRLabs Internet Innovation Centre NRC Inst. Biodiagnostics APEGM IEEE Winnipeg Sec. IEEE Canada & IEEE Manitoba Hydro Vansco Electron. Bristol Aerosp. Nygard Int. Norsat
Starting Page	776
Ending Page	781
File Size	527021
Page Count	6
File Format	PDF
ISBN	0780375149
ISSN	08407789
DOI	10.1109/CCECE.2002.1013040
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-12
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage Computer errors Power system faults Valves Power system simulation Design optimization Power engineering and energy Neural networks Constraint optimization Partitioning algorithms
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Neural Network Optimization for Hardware-Software Partitioning

A Novel Neural Network Search for Energy-Efficient Hardware-Software Partitioning

Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment

Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint

A comprehensive power restoration approach using rule-based method for 11kV distribution network

Digital Simulation of DC Links and AC Machines

New approach for solving optimization problems in economic load dispatch using Hopfield neural networks

A heuristic algorithm for power-network clustering

Parallel neural learning by iteratively adjusting error thresholds

Heuristic method in searching for global minima relative to high voltage ac error

Similar Documents

Neural Network Optimization for Hardware-Software Partitioning

A Novel Neural Network Search for Energy-Efficient Hardware-Software Partitioning

Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment

Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint

A comprehensive power restoration approach using rule-based method for 11kV distribution network

Digital Simulation of DC Links and AC Machines

New approach for solving optimization problems in economic load dispatch using Hopfield neural networks

A heuristic algorithm for power-network clustering

Parallel neural learning by iteratively adjusting error thresholds

Heuristic method in searching for global minima relative to high voltage ac error