NDLI: A bridge for a multiprocessor graphics system

Content Provider	IEEE Xplore Digital Library
Author	Balatsos, A. Aleksic, M.
Copyright Year	2002
Description	Author affiliation: ATI Technol. Inc., Toronto, Ont., Canada (Balatsos, A.; Aleksic, M.)
Abstract	The ongoing demand for better computer games has been the primary force driving graphics chips at an extreme pace. The new generation of graphics accelerators (GPUs) has migrated from 0.18 to 0.15/0.13-micron in recent years. They provide powerful floating point streaming engines with deep pipelining and operate at multiple pixels per clock. We describe a novel multiprocessor graphics system (MAX) and a specialized bridge that allows applications to scale performance for high-end graphics systems. Our system uses standard graphics processors with dedicated VLSI bridge chips for AGP/PCI bus support. Scalability can be achieved in two ways: by time multiplexing or by image parallelism. In time multiplexing mode, different GPUs render different frames keeping the command traffic the same as in the single GPU case. When load balancing is done by image parallelism, the image space is split between GPUs and each GPU renders only a dedicated image segment. The custom VLSI bridge supports parallel rendering by routing between GPUs and also by interfacing to the host CPU and main memory through the AGP4X bus (1 GB/s). It also contains enhanced features to facilitate the broadcast/routing of graphics data from the host.
Sponsorship	Dept. Electr. & Comput. Eng. Faculty of Graduate Studies Faculty of Eng. TRLabs Internet Innovation Centre NRC Inst. Biodiagnostics APEGM IEEE Winnipeg Sec. IEEE Canada & IEEE Manitoba Hydro Vansco Electron. Bristol Aerosp. Nygard Int. Norsat
Starting Page	646
Ending Page	650
File Size	421606
Page Count	5
File Format	PDF
ISBN	0780375149
ISSN	08407789
DOI	10.1109/CCECE.2002.1013017
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-12
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bridges Computer graphics Rendering (computer graphics) Very large scale integration Parallel processing Routing Engines Pipeline processing Clocks Scalability
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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