NDLI: Efficient parallel implementation of motion estimation on the Computational RAM architecture

Content Provider	IEEE Xplore Digital Library
Author	Ai, H. Li, N. Li, T. Mandal, M.K. Cockburn, B.F.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada (Ai, H.; Li, N.; Li, T.; Mandal, M.K.; Cockburn, B.F.)
Abstract	Motion estimation is the most computationally intensive task in present video compression standards. Parallel processing has proved to be an efficient approach for similar kinds of applications. In this paper, we propose two parallel implementations of block-based motion estimation for a massively-parallel, processor-in-memory hardware architecture known as Computational RAM (C-RAM). Our simulation study showed that, although the massive parallelism of C-RAM does potentially have great benefits, the use of embedded DRAM and bit-serial arithmetic reduced the achievable speed-up to about 4 compared to 733 MHz Pentium III machine.
Sponsorship	Dept. Electr. & Comput. Eng. Faculty of Graduate Studies Faculty of Eng. TRLabs Internet Innovation Centre NRC Inst. Biodiagnostics APEGM IEEE Winnipeg Sec. IEEE Canada & IEEE Manitoba Hydro Vansco Electron. Bristol Aerosp. Nygard Int. Norsat
Starting Page	609
Ending Page	613
File Size	488782
Page Count	5
File Format	PDF
ISBN	0780375149
ISSN	08407789
DOI	10.1109/CCECE.2002.1013011
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-12
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Concurrent computing Computer architecture Motion estimation Parallel processing Read-write memory Random access memory Streaming media Video sequences Video compression Hardware
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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