NDLI: Framed complexity analysis in SystemC for multi-level design space exploration

Content Provider	IEEE Xplore Digital Library
Author	Wellig, A. Zory, J.
Copyright Year	2003
Description	Author affiliation: Adv. Syst. Technol., STMicroelectronics, Geneva, Switzerland (Wellig, A.; Zory, J.)
Abstract	To guarantee efficient system-on-a-chip (SoC) solutions, design space exploration at various abstraction levels is needed. In this paper, we describe a simulation framework, which is particularly suited for multi-level exploration. Identifying the capturing of design metrics and their incorporation into an exploration framework as the main tasks to be resolved, we will propose a flexible monitoring tool implemented in SystemC to tackle the first item. We present a unified approach to capture and record behavioral, storage and communication characteristics at several abstraction levels of a typical SoC design flow. Figures such as increase in simulation time are included to characterize the developed tool. To address the design decision-making criteria, relevant design metrics are defined for each abstraction level. We distinguish among four distinct levels modeling algorithm and architecture transitions. Finally, iteration control aspects of Turbo decoders used in wireless systems serve as a case study.
Starting Page	416
Ending Page	423
File Size	327695
Page Count	8
File Format	PDF
ISBN	0769520030
DOI	10.1109/DSD.2003.1231975
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-09-01
Publisher Place	Turkey
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Space exploration Algorithm design and analysis Communication system control Design optimization Power system modeling Timing Delay estimation Digital systems Hardware Application software
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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