NDLI: Multiple voltage and frequency scheduling for power minimization

Content Provider	IEEE Xplore Digital Library
Author	Radhakrishnan, B. Venkatesan, M.
Copyright Year	2003
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Nevada, Las Vegas, NV, USA (Radhakrishnan, B.; Venkatesan, M.)
Abstract	This paper presents a resource-constrained scheduling scheme that minimizes power consumption for the case when the resources operate at multiple voltages and varied clock frequency. The resource constrained scheduling is achieved by performing a constructive, force-directed scheduling. The proposed algorithm consists of two phases, the voltage assignment phase and the clock frequency variation phase. It also includes a pre processing phase of node minimization, where redundant nodes are eliminated. In the first phase the assignment of voltages to each functional unit is performed based on its occurrence on the critical path. In the next stage, the clock frequency for each control step is varied by using the clock frequency of the maximum number of operation type in that control step. It is taken care that, the total execution delay does not exceed the timing constraint given by CP /spl les/ /spl alpha/ < 2CP, where '/spl alpha/' is a certain factor of the critical path time delay (CP). The power consumed in the level shifters is also taken into consideration. The power consumed is compared with the power consumed by operating all functional units at the maximum available voltage and maximum clock frequency. A power reduction of about 40-65% has been achieved.
Starting Page	279
Ending Page	284
File Size	300149
Page Count	6
File Format	PDF
ISBN	0769520030
DOI	10.1109/DSD.2003.1231949
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-09-01
Publisher Place	Turkey
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage Frequency High level synthesis Clocks Processor scheduling Very large scale integration Algorithm design and analysis Delay effects Logic circuits Hardware
Content Type	Text
Resource Type	Article

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