NDLI: Late Hardware/Software Partitioning by Using SystemC Functional Models

Content Provider	IEEE Xplore Digital Library
Author	Brunmayr, P. Haase, J. Schupfer, F.
Copyright Year	2009
Abstract	In this paper a partly unified hardware/software design flow is presented. It uses SystemC as system level design language and postpones the partitioning decision to a lower abstraction level by using a realization independent functional model. Especially the partitioning of data flow dominant tasks between hardware and software is simplified with this approach. Additionally, by using a C-based design language for hardware and software design, system simulations at different abstraction levels are simplified. In combination with the concept of high level synthesis, this design flow reduces the effort after the partitioning and thus also significantly reduces the extra effort of a possible repartitioning between hardware and software. As proof of concept the receiver components of a VoIP engine have been implemented. The data flow dominant RTP protocol has been realized on an FPGA and the results of different hardware/software partitionings are presented.
Starting Page	194
Ending Page	199
File Size	256361
Page Count	6
File Format	PDF
ISBN	9781424441549
DOI	10.1109/AMS.2009.18
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-25
Publisher Place	Indonesia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computational modeling FPGA VoIP Hardware/Software Codesign System-level design Signal Processing Software design Partitioning Asia Digital signal processing High level synthesis Space exploration Timing High Level Synthesis Hardware design languages Field programmable gate arrays SystemC
Content Type	Text
Resource Type	Article

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