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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Cherroun, H. Feautrier, P. |
| Copyright Year | 2007 |
| Description | Author affiliation: A.T. Univ., Laghouat (Cherroun, H.) |
| Abstract | Scheduling is an important technique in high-level synthesis to match application computations and hardware resources. Scheduling a whole program is not possible as too many constraints and objectives interact. We decompose high-level scheduling in three steps. Step 1: Coarse-grain scheduling tries to exploit parallelism and locality of the whole program (in particular in loops, possibly imperfectly nested) with a rough view of the target architecture. This produces a sequence of logical steps, each of which contains a pool of macro-tasks (with no loops). Step 2: Fine-grain scheduling refines each logical step by scheduling all its macro-tasks. Between both steps a resource assignation is done by mapping each macro-task independently. We uniformly expressed the data dependences and resource constraints. As most scheduling problems, scheduling tasks under resources constraints to minimize the total duration is NP-complete. Our goal here is to design strategy for reaching optimal solutions in reasonable time. Our algorithmic contribution is an exact branch-and-bound algorithm, where each evaluation is accelerated by both maximal and greedy clique computation. The effectiveness and efficiency of the approach are good, which is illustrated by means of some practical benchmarks. |
| Starting Page | 554 |
| Ending Page | 561 |
| File Size | 240957 |
| Page Count | 8 |
| File Format | |
| ISBN | 1424410304 |
| DOI | 10.1109/AICCSA.2007.370936 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-05-13 |
| Publisher Place | Jordan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Processor scheduling High level synthesis Hardware Parallel processing Acceleration Circuits Size measurement Scheduling algorithm Algorithm design and analysis Computer applications |
| Content Type | Text |
| Resource Type | Article |
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