NDLI: On tests to detect via opens in digital CMOS circuits

Content Provider	IEEE Xplore Digital Library
Author	Reddy, S.M. Pomeranz, I. Chen Liu
Copyright Year	2008
Description	Author affiliation: Univ. of Iowa, Iowa City, IA (Reddy, S.M.)
Abstract	We consider voltage based (logic) tests to detect complete opens in digital CMOS circuits. Open defects are known to be prevalent in the current VLSI technologies and vias are known to be the primary sites of interconnect opens. The voltage on a circuit node that is disconnected due to an open via is determined by several circuit parameters. As the feature size of VLSI circuits decreases, precise knowledge of the values of circuit parameters may be difficult, if not impossible, to obtain. Thus, it is important to develop methods to generate tests to detect opens that do not require accurate knowledge of circuit parameters. We propose new classes of tests to detect via opens with voltage based (logic) tests that are effective even with imprecise knowledge of circuit parameters. The proposed tests to detect an open via are constituted as a pair of constrained stuck-at fault tests for the circuit node affected by the open defect. One class of proposed tests called circuit parameter independent tests detect via opens even in the case of complete lack of knowledge of the circuit parameters. Experimental results demonstrate that high coverage of open vias can be obtained using the proposed constrained tests.
Starting Page	840
Ending Page	845
File Size	624689
Page Count	6
File Format	PDF
ISBN	9781605581156
ISSN	0738100X
DOI	10.1145/1391469.1391682
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Circuit testing CMOS digital integrated circuits Logic testing Voltage CMOS logic circuits Very large scale integration CMOS technology Integrated circuit interconnections Logic circuits Electrical fault detection constrained stuck-at tests Open defects DFT test generation
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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