NDLI: Transistor level gate modeling for accurate and fast timing, noise, and power analysis

Content Provider	IEEE Xplore Digital Library
Author	Raja, S. Varadi, F. Becer, M. Geada, J.
Copyright Year	2008
Description	Author affiliation: CLK Design Autom., Littleton, MA (Raja, S.; Varadi, F.; Becer, M.; Geada, J.)
Abstract	Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65 nm and below. Voltage waveform shapes are increasingly more difficult to represent as simple ramps due to highly resistive interconnects and Miller cap effects at receiver gates. Propagation of complex voltage waveforms, and accurate modeling of nonlinear driver and receiver effects in crosstalk noise analysis require accurate cell models. A good cell model should be independent of input waveform and output load, should be easy to characterize and should not increase the complexity of a cell library with high-dimensional look-up tables. At the same time, it should provide high accuracy compared to SPICE for all analysis scenarios including multiple-input switching, and for all cell types and cell arcs, including those with high stacks. It should also be easily extendable for use in statistical STA and noise analysis, and one should be able to simulate it fast enough for practical use in multi-million gate designs. In this paper, we present a gate model built from fast transistor models (FXM) that has all the desired properties. Along with this model, we also present a multithreaded timing traversal approach that allows one to take advantage of the high accuracy provided by the FXM, at traditional STA speeds. Results are presented using a fully extracted 65 nm TSMC technology.
Starting Page	456
Ending Page	461
File Size	593011
Page Count	6
File Format	PDF
ISBN	9781605581156
ISSN	0738100X
DOI	10.1145/1391469.1391588
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Timing Noise level Crosstalk Voltage Noise shaping Design automation Capacitance Permission Shape Libraries multi threaded gate modeling timing crosstalk statistical
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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