NDLI: Scalable min-register retiming under timing and initializability constraints

Content Provider	IEEE Xplore Digital Library
Author	Hurst, A.P. Mishchenko, A. Brayton, R.K.
Copyright Year	2008
Description	Author affiliation: California Univ., Berkeley, CA (Hurst, A.P.; Mishchenko, A.; Brayton, R.K.)
Abstract	We demonstrate that a maximum-flow-based approach to register-minimization is a useful platform for incorporating varied design constraints. In this work, we extend the flow-based formulation to include timing constraints and to guarantee the existence of an equivalent initial state. Reducing the register count is motivated by positive consequences for physical design, verification, and power consumption, but it is critically necessary for synthesis that these timing and functionality requirements are also met. Our solution is optimum in the number of registers under either or both constraints and also possesses several other distinct advantages: the runtime is significantly faster than comparable techniques, the algorithm is capable of early termination with a timing-feasible solution, and both maximum and minimum path constraints can be specified.
Starting Page	534
Ending Page	539
File Size	535584
Page Count	6
File Format	PDF
ISBN	9781605581156
ISSN	0738100X
DOI	10.1145/1391469.1391604
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Timing Registers Clocks Minimization Logic design Runtime Energy consumption Algorithm design and analysis Computer networks Circuits Min-Area Retiming Sequential Optimization Initial State
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Scalable min-register retiming under timing and initializability constraints

Scalable min-register retiming under timing and initializability constraints (2008).

Fast Minimum-Register Retiming via Binary Maximum-Flow

Scalable Min-Area Retiming Under Simultaneous Timing and Initial State Constraints

Scalable min-area retiming under simultaneous timing and initial state constraints.

Retiming for soft error minimization under error-latching window constraints

An efficient retiming algorithm under setup and hold constraints

Retiming sequential circuits with multiple register classes

An efficient incremental algorithm for min-area retiming

Scalable min-register retiming under timing and initializability constraints

Similar Documents

Scalable min-register retiming under timing and initializability constraints

Scalable min-register retiming under timing and initializability constraints (2008).

Fast Minimum-Register Retiming via Binary Maximum-Flow

Scalable Min-Area Retiming Under Simultaneous Timing and Initial State Constraints

Scalable min-area retiming under simultaneous timing and initial state constraints.

Retiming for soft error minimization under error-latching window constraints

An efficient retiming algorithm under setup and hold constraints

Retiming sequential circuits with multiple register classes

An efficient incremental algorithm for min-area retiming

Scalable min-register retiming under timing and initializability constraints