NDLI: TETA: transistor-level engine for timing analysis

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TETA: transistor-level engine for timing analysis

Content Provider	IEEE Xplore Digital Library
Author	Dartu, F. Pileggi, L.T.
Copyright Year	1998
Description	Author affiliation: Strategic CAD Labs., Intel Corp., USA (Dartu, F.)
Abstract	TETA is an interconnect-centric waveform calculator that was optimized to achieve the utmost efficiency for analyzing logic stages comprised of transistors and large coupled RC(L) interconnect models. TETA applies a novel compaction for the transistor clusters and employs successive chord iterations to solve the resulting nonlinear equations. These algorithms permit the use of simple SIMO (single input multi-output) N-port interconnect models since macromodel passivity is not required. The successive chord analysis also enables TETA to avoid the N-port matrix factorization during nonlinear iterations and allows the use of simple table look-up models for MOS devices. Complex gates and nonlinear capacitors can be handled without loss of generality.
Starting Page	595
Ending Page	598
File Size	480636
Page Count	4
File Format	PDF
ISBN	0897919645
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-06-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Engines Timing Integrated circuit interconnections Logic Permission Compaction Semiconductor device modeling CMOS technology SPICE Time of arrival estimation
Content Type	Text
Resource Type	Article

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