NDLI: Potential NRG: placement with incomplete data

Content Provider	IEEE Xplore Digital Library
Author	Maogang Wang Banerjee, P. Sarrafzadeh, M.
Copyright Year	1998
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA (Maogang Wang)
Abstract	Traditional placement problems are studied under a fully specified cell library and a complete netlist. However, in the first, e.g., 2 years of a 2-3 year microprocessor design cycle, the detailed netlist is unavailable. For area and performance estimation, layout must nevertheless be done with incomplete information. Another source of incompleteness comes from reuse of instances from earlier design generations; these instances and their parameters will change as the project evolves. The problem of placement with incomplete data (PID) can be abstracted as having to place a circuit when p/sub c/% of the cells and p/sub n/% of the nets are missing. The key challenge in PID is how to add missing cells and nets. In this paper, two "patching-methods" for adding missing nets and cells are proposed. The methods are called abstraction and fusion. Experimental results are very interesting and illustrative. First, they show that PID is a difficult problem and an arbitrary (and perhaps intuitively sound) method may not produce high-quality results. Experiments verify that the abstraction method is a very good predictor and that fusion is not because circuits produced by abstraction attain much of the properties of the original circuits. Summary Table 3 in Section 4 shows that when a circuit has 10% incompleteness, abstraction can predict the final total wirelength with an error of 5.8%, while fusion has a 67.8% error in predicting the wirelength in the same circuit.
Starting Page	279
Ending Page	282
File Size	464581
Page Count	4
File Format	PDF
ISBN	0897919645
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-06-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Libraries Circuits Cost function Permission Very large scale integration Microprocessors Simulated annealing Minimization Hardware
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Optimization of Cost Function with Cell Library Placement of VLSI Circuits Using Simulated Annealing

Module placement for analog layout using the sequence-pair representation

A new simultaneous partitioning and chip placement approach based on simulated annealing

Modified SA algorithm for wirelength minimization in VLSI circuits

KAHLUA: A Hierarchical Circuit Disassembler

An easy tune-up exponentially fast annealer for high-quality analog module placement

Array Optimization for VLSI Synthesis

Fast timing driven placement using tabu search

Congestion minimization during placement without estimation

Potential NRG: placement with incomplete data

Similar Documents

Optimization of Cost Function with Cell Library Placement of VLSI Circuits Using Simulated Annealing

Module placement for analog layout using the sequence-pair representation

A new simultaneous partitioning and chip placement approach based on simulated annealing

Modified SA algorithm for wirelength minimization in VLSI circuits

KAHLUA: A Hierarchical Circuit Disassembler

An easy tune-up exponentially fast annealer for high-quality analog module placement

Array Optimization for VLSI Synthesis

Fast timing driven placement using tabu search

Congestion minimization during placement without estimation

Potential NRG: placement with incomplete data