NDLI: Asynchronous interface specification, analysis and synthesis

Content Provider	IEEE Xplore Digital Library
Author	Kishinevsky, M. Cortadella, J. Kondratyev, A.
Copyright Year	1998
Description	Author affiliation: Intel Corp., Hillsboro, OR, USA (Kishinevsky, M.)
Abstract	Interfaces, by nature, are often asynchronous since they serve for connecting multiple distributed modules/agents without common clock. However the most recent developments in the theory of asynchronous design in the areas of specifications, models, analysis, verification, synthesis, technology mapping, timing optimization and performance analysis are not widely known and rarely accepted by industry. The goal of this tutorial is to fill this gap and to present an overview of one popular systematic design methodology for design of asynchronous interface controllers. This methodology is based on using Petri nets (PN) a formal model that, from the engineering standpoint, is a formalization of timing diagrams (waveforms) and from the system designer standpoint is a concurrent state machine, in which local components can perform independent or interdependent concurrent actions, changing their local states asynchronously. We will introduce this model informally based on a simple example: a VME-bus controller serving reads from a device to a bus and writes from the bus into the device.
Starting Page	2
Ending Page	7
File Size	673161
Page Count	6
File Format	PDF
ISBN	0897919645
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-06-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Performance analysis Timing Design methodology Joining processes Clocks Control system synthesis Design optimization Electrical equipment industry Control systems Petri nets
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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