NDLI: Floorplanning for 3-D VLSI design

Content Provider	IEEE Xplore Digital Library
Author	Lei Cheng Liang Deng Wong, M.D.F.
Copyright Year	2005
Description	Author affiliation: Coordinated Sci. Lab., Illinois Univ., Urbana-Champaign, IL, USA (Lei Cheng; Liang Deng; Wong, M.D.F.)
Abstract	In this paper, we present a floorplanning algorithm for 3D ICs. The problem can be formulated as that of packing a given set of 3D rectangular blocks while minimizing a suitable cost function. Our algorithm is based on a generalization of the classical 2D slicing floorplans to 3D slicing floorplans. A new encoding scheme of slicing floorplans (2D/3D) and its associated set of moves form the basis of the new simulated annealing based algorithm. The best-known algorithm for packing 3D rectangular blocks is based on simulated annealing using sequence-triple floorplan representation. Experimental results show that our algorithm produces packing results on average 3% better than the sequence-triple-based algorithm under the same annealing parameters, and our algorithm runs much faster (17 times for problems containing 100 blocks) than the sequence-triple. Moreover, our algorithm can be extended to consider various types of placement constraints and thermal distribution while the existing sequence-triple-based algorithm does not have such capabilities. Finally, when specializing to 2D problems, our algorithm is a new 2D slicing floorplanning algorithm. We are excited to report the surprising results that our new 2D floorplanner has produced slicing floorplans for the two largest MCNC benchmarks ami33 and ami49 which have the smallest areas (among all slicing/nonslicing floorplanning algorithms) ever reported in the literature.
Sponsorship	Chinese Inst. of Electron
Starting Page	405
Ending Page	411
File Size	1179997
Page Count	7
File Format	PDF
ISBN	0780387368
DOI	10.1109/ASPDAC.2005.1466197
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-01-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Integrated circuit interconnections Simulated annealing CMOS technology Integrated circuit technology Three-dimensional integrated circuits Testing Computer science Cost function Encoding
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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