NDLI: FSM re-engineering and its application in low power state encoding

Content Provider	IEEE Xplore Digital Library
Author	Lin Yuan Gang Qu Villa, T. Sangiovanni-Vincentelli, A.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA (Lin Yuan; Gang Qu)
Abstract	We propose finite state machine (FSM) re-engineering, a performance enhancement framework for FSM synthesis and optimization procedure. We start with any traditional FSM synthesis and optimization procedure; then reconstruct a functionally equivalent but topologically different FSM based on the optimization objective; and conclude with another round of FSM synthesis and optimization (can be the same procedure) on the newly constructed FSM. This allows us to explore a larger solution space that includes synthesis solutions to the functionally equivalent FSMs instead of only the original FSM, making it possible to obtain solutions better than the optimal ones for the original FSM. Guided by the result of the first round FSM synthesis, the solution space exploration process can be rapid and cost-efficient. To demonstrate this framework, we develop a genetic algorithm and a fast heuristic to reengineer a low power state encoding procedure POW3 (Benini and Micheli, 1995). On average, POW3 can reduce the switching activity by 12% over nonpower-driven state encoding schemes on the MCNC FSM benchmarks. We then reengineer these benchmarks by the proposed genetic algorithm and heuristic respectively. When we apply POW3 to the reengineered FSMs, we observe an additional 8.9% and 6.0% switching activity reduction. This translates to an average of 7.9% energy reduction with little area increase. Finally, we obtain the optimal low power coding for benchmarks of small size from an integer linear programming formulation. We find that the POW3-encoded original FSMs are 27.0% worse than the optimal, but this number drops to 6.7% when we apply POW3 to the reengineered FSMs.
Sponsorship	Chinese Inst. of Electron
Starting Page	254
Ending Page	259
File Size	1159338
Page Count	6
File Format	PDF
ISBN	0780387368
DOI	10.1109/ASPDAC.2005.1466169
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-01-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Encoding Automata Genetic algorithms Logic testing Minimization Power dissipation Switching circuits Educational institutions Space exploration Integer linear programming
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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