NDLI: Thermal-driven multilevel routing for 3D ICs

Content Provider	IEEE Xplore Digital Library
Author	Cong, J. Yan Zhang
Copyright Year	2005
Description	Author affiliation: Dept. of Comput. Sci., UCLA, Los Angeles, CA, USA (Cong, J.; Yan Zhang)
Abstract	3D IC has a great potential for improving circuit performance and degree of integration. It is also an attractive platform for system-on-chip or system-in-package solutions. A critical issue in 3D circuit design is heat dissipation. In this paper we propose an efficient 3D multilevel routing approach that includes a novel through-the-silicon via (TS-via) planning algorithm. The proposed approach features an adaptive lumped resistive thermal model and a two-step multilevel TS-via planning scheme. Experimental results show that with multilevel TS-via planning, the thermal-driven approach can reduce the maximum temperature to the required temperature with reasonable wirelength increase. Compared to a post processing approach for dummy TS-via insertion, to achieve the same required temperature, our approach uses 80% fewer TS-vias. To our knowledge, this proposed approach is the first thermal-driven 3D routing algorithm.
Sponsorship	Chinese Inst. of Electron
Starting Page	121
Ending Page	126
File Size	1276096
Page Count	6
File Format	PDF
ISBN	0780387368
DOI	10.1109/ASPDAC.2005.1466143
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-01-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Three-dimensional integrated circuits Circuit synthesis Temperature System-on-a-chip Thermal resistance Integrated circuit packaging Thermal conductivity Algorithm design and analysis Finite difference methods
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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