NDLI: An integrated approach for increasing the soft-error detection capabilities in SoCs processors

Content Provider	IEEE Xplore Digital Library
Author	Bernardi, P. Bolzani, L. Rebaudengo, M. Reorda, M.S. Violante, M.
Copyright Year	2005
Description	Author affiliation: Politecnico di Torino, Italy (Bernardi, P.; Bolzani, L.; Rebaudengo, M.; Reorda, M.S.; Violante, M.)
Abstract	Software implemented hardware fault tolerance (SIHFT) techniques are able to detect most of the transient and permanent faults during the usual system operations. However, these techniques are not capable to detect some transient faults affecting processor memory elements such as state registers inside the processor control unit, or temporary registers inside the arithmetic and logic unit. In this paper, we propose an integrated (hardware and software) approach to increase the fault detection capabilities of software techniques by introducing a limited hardware redundancy. Experimental results are reported showing the effectiveness of the proposed approach in covering soft-errors affecting the processor memory elements and escaping to purely software approaches.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council IEEE Comput. Soc. Tech. Comm. on Fault-Tolerant Comput
Starting Page	445
Ending Page	453
File Size	263712
Page Count	9
File Format	PDF
ISBN	0769524648
ISSN	15505774
DOI	10.1109/DFTVS.2005.17
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Fault detection Circuit faults Redundancy Registers Fault tolerant systems Process control Arithmetic Logic Computer aided manufacturing
Content Type	Text
Resource Type	Article

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