NDLI: Incorporating error detection and online reconfiguration into a regular architecture for the advanced encryption standard

Content Provider	IEEE Xplore Digital Library
Author	Breveglieri, L. Koren, I. Maistri, P.
Copyright Year	2005
Description	Author affiliation: Dept. of Electron. & Inf. Technol., Politecnico di Milano, Italy (Breveglieri, L.)
Abstract	Fault injection based attacks on cryptographic devices aim at recovering the secret keys by inducing an error in the computation process. They are now considered a real threat and countermeasures against them must be taken. In this paper, we describe an extension to an existing AES architecture proposed by Mangard et al. (2003), which provides error detection and fault tolerance by exploiting the high regularity of the architecture. The proposed design is capable of performing online error detection and reconfiguring internal data paths to protect against faults occurring in the computation process. We also describe how different redundancy levels provide protection against different numbers of errors. The presented design incorporating fault detection and tolerance has the same throughput as the base architecture but incurs a nonnegligible area overhead. This overhead is about 40% for the fault detection circuitry and 134% for the entire fault detection and tolerance (through reconfiguration). Although quite high, this overhead is still lower than for reference solutions such as duplication (providing detection) and triple modular redundancy (providing fault masking).
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council IEEE Comput. Soc. Tech. Comm. on Fault-Tolerant Comput
Starting Page	72
Ending Page	80
File Size	247892
Page Count	9
File Format	PDF
ISBN	0769524648
ISSN	15505774
DOI	10.1109/DFTVS.2005.41
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Cryptography Computer architecture Throughput Fault detection Electrical fault detection Circuit faults Redundancy Hardware Computer errors Protection
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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