NDLI: Early error detection in systems-on-chip for fault-tolerance and at-speed debugging

Content Provider	IEEE Xplore Digital Library
Author	Sogomonyan, E.S. Morosov, A. Gossel, M. Singh, A. Rzeha, J.
Copyright Year	2001
Abstract	In this paper we propose a new method for the design of duplex fault-tolerant systems with early error detection and high availability. All the scannable memory elements (flip-flops) of the duplicated system are implemented as multimode memory elements according to Singh et al. (1999), thus allowing during normal operation the accumulation of a signature of its states in its scan-paths. By continuously comparing a 1-bit sequence of the compacted scan-out outputs of the accumulated signatures of the duplicated systems an error can be already detected and a recovery procedure started before an erroneous result appears at the system outputs when a computations is completed. The accumulation of a signature during normal operation can also be used for debugging at-speed. For this application the system need not be duplicated.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	184
Ending Page	189
File Size	620703
Page Count	6
File Format	PDF
ISBN	0769511228
DOI	10.1109/VTS.2001.923437
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-04-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault detection Fault tolerant systems Debugging Circuit faults Circuit testing Redundancy System testing Hardware Integrated circuit testing Computer errors
Content Type	Text
Resource Type	Article

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