NDLI: Duplication-based concurrent error detection in asynchronous circuits: shortcomings and remedies

Content Provider	IEEE Xplore Digital Library
Author	Verdel, T. Makris, Y.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA (Verdel, T.; Makris, Y.)
Abstract	Concurrent error detection (CED) methods are typically employed to provide an indication of the operational health of synchronous circuits during normal functionality. Existing CED techniques, however, require modification in order to be successfully adapted to asynchronous designs. We discuss the limitations of duplication, the simplest CED method, when applied to asynchronous circuits. We demonstrate that such limitations arise mainly due to comparison synchronization issues and inadequate detection of performance-related errors. We propose a circuit that alleviates the difficulties associated with comparison synchronization and we introduce a methodology that enables detection of errors that do not result in logic discrepancies and, thus, may not be detected through comparison. The proposed techniques are illustrated on example circuits, revealing their ability to render concurrently testable asynchronous designs.
Starting Page	345
Ending Page	353
File Size	391601
Page Count	9
File Format	PDF
ISBN	0769518311
ISSN	15505774
DOI	10.1109/DFTVS.2002.1173531
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-11-06
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Asynchronous circuits Circuit testing Circuit faults Synchronization Electrical fault detection Fault detection Clocks Monitoring Design automation Logic circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in