NDLI: Manufacturability analysis of analog CMOS ICs through examination of multiple layout solutions

Content Provider	IEEE Xplore Digital Library
Author	Khademsameni, P. Syrzycki, M.
Copyright Year	2002
Description	Author affiliation: Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada (Khademsameni, P.; Syrzycki, M.)
Abstract	Introduces a methodology for the manufacturability analysis of analog CMOS ICs. The methodology is based on examination of several layout solutions of a single circuit. A critical area approach to evaluate a theoretical random-defect limited yield is applied for each layout solution. Users can choose the appropriate layout solution after comparing the theoretical yield values and considering results obtained from economical post-layout simulation tools. The theoretical yield has been proposed as one of possible quality factors in the design for manufacturability. The multi-layout approach, which is presented here, has been implemented in a CAD tool (ALDAC). The use of this CAD tool for layout generation and analysis of circuit manufacturability will be presented here.
Starting Page	3
Ending Page	11
File Size	373924
Page Count	9
File Format	PDF
ISBN	0769518311
ISSN	15505774
DOI	10.1109/DFTVS.2002.1173496
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-11-06
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS analog integrated circuits Analog integrated circuits Integrated circuit layout Pulp manufacturing Fabrication CMOS process Manufacturing processes Integrated circuit modeling Circuit simulation Q factor
Content Type	Text
Resource Type	Article

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