NDLI: Effect of static power dissipation in burn-in environment on yield of VLSI

Content Provider	IEEE Xplore Digital Library
Author	Vassighi, A. Semenov, O. Sachdev, M. Keshavarzi, A.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada (Vassighi, A.; Semenov, O.; Sachdev, M.)
Abstract	The leakage power is expected to increase with scaling of CMOS technology. The increased leakage is a strong function of the elevated temperature and voltage stress. As a consequence; under the burn-in (BI) conditions the elevated leakage power may cause increased post burn-in fallout. In this paper the impact of elevated leakage and technology scaling in burn-in environment on post BI yield is analyzed. We have also shown that to maintain a constant post-BI yield loss, the burn-in temperature should go down by 10/spl deg/C for each technology generation. We also show that at static burn-in conditions, the die temperature is increased exponentially and range of optimal stressed voltage and temperature for fixed post burn-in yield loss is reduced significantly, when CMOS technology is aggressively scaled down.
Starting Page	12
Ending Page	19
File Size	1165691
Page Count	8
File Format	PDF
ISBN	0769518311
ISSN	15505774
DOI	10.1109/DFTVS.2002.1173497
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-11-06
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration CMOS technology Voltage Bismuth Power dissipation Thermal resistance Stress Temperature distribution Circuit testing Immune system
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in