NDLI: Scan architecture for shift and capture cycle power reduction

Content Provider	IEEE Xplore Digital Library
Author	Rosinger, P.M. Al-Hashimi, B.M. Nicolici, N.
Copyright Year	2002
Description	Author affiliation: Dept. of Electron. & Comput. Sci., Southampton Univ., UK (Rosinger, P.M.; Al-Hashimi, B.M.)
Abstract	Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and improving the yield. Scan architectures represent the most used approach for testing digital integrated circuits. While several methods have been proposed for reducing the power dissipation due to scan shifting, very little work has been done towards reducing the power dissipation during the capture cycles. This paper proposes a method of transforming a typical scan architecture for reducing the power dissipation during both the shifting cycle and the capture cycle. The basic idea is to split the the scan chain into multiple length-balanced partitions and to enable only one partition at each test clock. This way, instead of having all the scan cells active at the same time, only a fraction of them will be active in each test clock cycle, which will reduce substantially the power dissipation in the circuit under test. Unlike previously proposed methods for shifting power reduction based on scan chain partitioning which use a single capture clock per test cycle, our approach uses multiple capture clocks per test cycle, which allows enabling only a fraction of the scan chain during each shift or capture clock, thus reducing the switching activity in the circuit under test not only during shifting but also during capture. Therefore, the proposed method represents an unified solution for reducing both shifting and capture power dissipation during scan-based test. The proposed method also allows full reuse of the test vectors of the original scan architecture.
Starting Page	129
Ending Page	137
File Size	295984
Page Count	9
File Format	PDF
ISBN	0769518311
ISSN	15505774
DOI	10.1109/DFTVS.2002.1173509
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-11-06
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Power dissipation Clocks Digital integrated circuits Integrated circuit testing Logic circuits Integrated circuit yield Switching circuits Controllability Observability
Content Type	Text
Resource Type	Article

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