NDLI: A fast adder-based multiplication unit for customised digital signal processors

Content Provider	IEEE Xplore Digital Library
Author	De Vos, L. Jain, R. De Man, H. Ulbrich, W.
Copyright Year	1986
Description	Author affiliation: IMEC, Leuven, Belgium (De Vos, L.)
Abstract	This paper presents the design of a parameterisable multiplication-accumulation unit for integrated digital signal processing devices. It is especially suited for macrocell based customised signal processors as proposed by [1]. The complete architecture including the data-path and associated control are described. Estimates of the chip area and speed are presented based on a 3 µm CMOS cell library. The essential advantage of the proposed design is that the time taken for ann-bit byn-bit multiplication of two signals is(n/4)+1processor cycles where each cycle only requires the shifted values of two numbers to be added to a third number using a carry-save and a carry-propagate adder. Compared to conventional shifter-adder based multiplication units this leads to an improvement in the throughput by approximately a factor 4 with one-third the area of a fully hardwired array multiplier for a 16×16 bit multiplication.
Starting Page	2163
Ending Page	2166
File Size	151264
Page Count	4
File Format	PDF
DOI	10.1109/ICASSP.1986.1169258
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1986-04-07
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processors Signal processing algorithms Signal processing Adders Throughput Signal design Digital signal processing chips Digital integrated circuits Macrocell networks Software libraries
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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