NDLI: Fault-tolerant digital filtering structures for wafer scale VLSI

Content Provider	IEEE Xplore Digital Library
Author	Redinbo, R.
Copyright Year	1986
Description	Author affiliation: University of California, Davis, California (Redinbo, R.)
Abstract	Digital filtering architectures that simultaneously offer advantages for wafer VLSI fabrication and contain distributed error-control are presented. Such structures require parallelism as well as inherent error-control capabilities because VLSI implementations are susceptible to temporary and intermittent hardware errors such as soft fails. Convolutions are implemented by finite field arithmetic subsections, where the operations in the various subsections are equivalent to polynomial multiplications, leading to the natural introduction of cyclic codes in the basic architecture. A polynomial expansion technique permits powerful cyclic subcodes to be introduced in each parallel subsection resulting from such a decomposition. Locations for error control within the architectures are examined, and several approaches for combatting failures are detailed.
Starting Page	1189
Ending Page	1192
File Size	117613
Page Count	4
File Format	PDF
DOI	10.1109/ICASSP.1986.1168791
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1986-04-07
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Digital filters Filtering Very large scale integration Fabrication Hardware Convolutional codes Galois fields Arithmetic Polynomials
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Hybrid WHT-RNS architectures for fault tolerant adaptive filtering

Bit serial fault tolerant architectures for convolution and polynomial evaluation

Systolic VLSI implementations of a Galois field arithmetic algorithms

VLSI architecture for datapath integration of arithmetic over GF(2/sup m/) on digital signal processors

RNS Digital Filtering Structures for Wafer-Scale Integration

High-speed VLSI design for Montgomery inverse over GF(2/sup m/)

Fault Tolerant Signal Processing for Masking Transient Errors in VLSI Signal Processors

An efficient fault-tolerant VLSI architecture using parallel evolvable hardware technology

Yield and layout issues in fault tolerant VLSI architectures

Fault-tolerant digital filtering structures for wafer scale VLSI

Similar Documents

Hybrid WHT-RNS architectures for fault tolerant adaptive filtering

Bit serial fault tolerant architectures for convolution and polynomial evaluation

Systolic VLSI implementations of a Galois field arithmetic algorithms

VLSI architecture for datapath integration of arithmetic over GF(2/sup m/) on digital signal processors

RNS Digital Filtering Structures for Wafer-Scale Integration

High-speed VLSI design for Montgomery inverse over GF(2/sup m/)

Fault Tolerant Signal Processing for Masking Transient Errors in VLSI Signal Processors

An efficient fault-tolerant VLSI architecture using parallel evolvable hardware technology

Yield and layout issues in fault tolerant VLSI architectures

Fault-tolerant digital filtering structures for wafer scale VLSI