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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Williams, F. |
| Copyright Year | 1986 |
| Description | Author affiliation: TRW LSI Products Division, La Jolla, California (Williams, F.) |
| Abstract | This paper reports on the results obtained by simulating 1024, 256, and 128 point complex-to-complex Fast Fourier Transforms with four different floating point formats: the IEEE P754 Rev.10 standard, the MIL-STD-1750A standard, the TRW 22-bit DSP format, and the Hitachi 16/20-bit format. Since many existing systems use a sixteen-bit format, performance of a sixteen bit format (with block floating point where appropriate) was used as a baseline for comparison. The results were evaluated for bias and variance (in the form of signal-to-noise ratio) for all functions. The performance of FIR and IIR filters was analyzed for the same numerical representations. |
| Starting Page | 2899 |
| Ending Page | 2902 |
| File Size | 133183 |
| Page Count | 4 |
| File Format | |
| DOI | 10.1109/ICASSP.1986.1168605 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1986-04-07 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Floating-point arithmetic Very large scale integration Dynamic range IIR filters FETs Finite impulse response filter Digital signal processing Signal to noise ratio Intermodulation distortion Passband |
| Content Type | Text |
| Resource Type | Article |
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