NDLI: Wafer Scale Integration Enabling Space Science

Content Provider	IEEE Xplore Digital Library
Author	Wesolek, D.M. Darrin, M.A.G. Osiander, R.
Copyright Year	2008
Description	Author affiliation: Appl. Phys. Lab., Johns Hopkins Univ., Laurel, MD (Wesolek, D.M.; Darrin, M.A.G.; Osiander, R.)
Abstract	Wafer scale integration enables the ability to miniaturize space craft instrument builds. We use the term wafer scale to indicate a packaging concept where the wafer is the substrate eliminating the use of individually packaged microstructures. The key here is the combination of advanced integration and miniaturization. The Johns Hopkins University Applied Physics Laboratory (JHUAPL) in collaboration with the US Air Force Academy is building a wafer integrated plasma spectrometer (WISPER) for mapping missions. The fabrication of the WISPER instrument suite uses a number of Micro Electro Mechanical Systems (MEMS) and micro electronics fabrication technologies. JHUAPL has successfully demonstrated these approaches in the fabrication of the single instrument currently in orbit on the FalconSat-3 mission. This instrument is a Flat Plasma Spectrometer (FlaPS) which includes a sensor-head array, printed circuit board with amplifier array electronics, power supply, and chassis which occupies a volume of approximately 400 $cm^{3}$ in a 0.5 kg, 700 mW package. The sensor head array is fabricated and assembled at the wafer-level and stacked in a planar geometry. Together with common electronics to control the array, our design takes advantage of emerging micro- fabrication techniques including deep reactive ion etching, laser machining, and wire electrical discharge machining, as well as advanced electronic die assembly and packaging methods. Innovations in packaging combined with etch process steps from the micro-fabrication industry allow for novel instrument builds which will open up the realm of nano sats and cubesat in mapping missions. This paper reviews the combination of manufacturing methods, material combinations and packaging techniques that can be applied to miniaturizing space instrumentation. This work is representative of the next generation of space instruments that will be enablers for smaller and more cost effective missions.
Starting Page	1
Ending Page	7
File Size	826899
Page Count	7
File Format	PDF
ISBN	9781424414871
ISSN	1095323X
DOI	10.1109/AERO.2008.4526476
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-03-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wafer scale integration Instruments Sensor arrays Electronics packaging Fabrication Packaging machines Plasma applications Spectroscopy Assembly Etching
Content Type	Text
Resource Type	Article
Subject	Aerospace Engineering Space and Planetary Science

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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