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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Coates, W.S. Lexau, J.K. Jones, I.W. Fairbanks, S.M. Sutherland, I.E. |
| Copyright Year | 2001 |
| Description | Author affiliation: Sun Microsyst. Labs., Palo Alto, CA, USA (Coates, W.S.) |
| Abstract | This paper describes a working chip, called FLEETzero, built to test an asynchronous switch fabric. The switch fabric transports 8-bit data items from any of eight sources to any of eight destinations. Measured throughput corresponds to approximately six gate-delays per data item, which in its 0.35 micron technology is in excess of 1.2 Giga-Data-Items per second (GDI/s); the corresponding latency through seven stages from source to destination is less than 4 nanoseconds. FLEETzero demonstrates a new family of high speed asynchronous control circuits, especially data-controlled branch and merge circuits that form the switch fabric. The FLEET concept may also herald a paradigm shift for computers. This new paradigm emphasizes data movement as the core action and contrasts with the traditional op code paradigm that focuses attention on logic and arithmetic instructions. The new paradigm promises outstanding throughput and many opportunities for optimization. |
| Sponsorship | IEEE Comput. Soc. Tech. Committee on VLSI |
| Starting Page | 173 |
| Ending Page | 182 |
| File Size | 784142 |
| Page Count | 10 |
| File Format | |
| ISBN | 0769510345 |
| ISSN | 15228681 |
| DOI | 10.1109/ASYNC.2001.914081 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-03-11 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic Switches Programming profession Fabrics Throughput Delay Arithmetic Circuits Costs Wires |
| Content Type | Text |
| Resource Type | Article |
| Subject | Engineering |
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