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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yakovlev, A. Xia, F. Shang, D. |
| Copyright Year | 2001 |
| Description | Author affiliation: Dept. of Comput. Sci., Newcastle upon Tyne Univ., UK (Yakovlev, A.) |
| Abstract | This paper describes the synthesis and hardware implementation of a signal-type asynchronous data communication mechanism (ACM). Such an ACM can be used in systems where a data-driven ("lazy") logic must be interfaced with a time-driven ("busy") environment. A new classification system for ACMs is introduced. The conceptual definition of the signal ACM (called simply "Signal") is refined using Petri net techniques. Based on this, a more precise, state graph specification of a two-slot signal is then constructed. Using the theory of regions, a Petri net specification of the ACM is synthesized from the state graph. The Petri net model is then translated into a hardware implementation, which is entered into Cadence tools. Simulation results show that the hardware does conform to the definitions and specifications. The techniques employed in this work are potentially useful in the development of an automated process of synthesising similar systems. |
| Sponsorship | IEEE Comput. Soc. Tech. Committee on VLSI |
| Starting Page | 127 |
| Ending Page | 136 |
| File Size | 939066 |
| Page Count | 10 |
| File Format | |
| ISBN | 0769510345 |
| ISSN | 15228681 |
| DOI | 10.1109/ASYNC.2001.914076 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-03-11 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Signal synthesis Data communication Writing Hardware Access protocols Logic Yarn Timing |
| Content Type | Text |
| Resource Type | Article |
| Subject | Engineering |
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