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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Peeters, A. Van Berkel, K. |
| Copyright Year | 2001 |
| Description | Author affiliation: Philips Res. Lab., Eindhoven, Netherlands (Peeters, A.) |
| Abstract | We present the synchronous implementation of handshake circuits as an extra feature in the otherwise asynchronous design flow based on Tangram. This synchronous option can be used in the mapping onto FPGAs or as a fallback option to provide a circuit that is easier to test and integrate in a synchronous environment. When single-rail and synchronous realizations of the same handshake circuit are compared, the synchronous versions typically require fewer state-holding elements, occupy less area, have similar performance, but consume significantly more power (in the examples studied up to a factor four). Synchronous handshake circuits provide a means to study clock-gating techniques based on the synthesis starting from a behavioral-level specification. In addition, the study provides hints as to where the asynchronous handshake circuits may be optimized further. |
| Sponsorship | IEEE Comput. Soc. Tech. Committee on VLSI |
| Starting Page | 86 |
| Ending Page | 95 |
| File Size | 911983 |
| Page Count | 10 |
| File Format | |
| ISBN | 0769510345 |
| ISSN | 15228681 |
| DOI | 10.1109/ASYNC.2001.914072 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-03-11 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Clocks Field programmable gate arrays Protocols Circuit testing Wire Laboratories Circuit synthesis Design optimization Asynchronous circuits Libraries |
| Content Type | Text |
| Resource Type | Article |
| Subject | Engineering |
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