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  1. International Symposium on Advanced Research in Asynchronous Circuits and Systems.
  2. Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001
  3. PCA-1: a fully asynchronous, self-reconfigurable LSI
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2015 21st IEEE International Symposium on Asynchronous Circuits and Systems
2014 20th IEEE International Symposium on Asynchronous Circuits and Systems
2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems
2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems
2011 17th IEEE International Symposium on Asynchronous Circuits and Systems
2010 IEEE Symposium on Asynchronous Circuits and Systems
2009 15th IEEE Symposium on Asynchronous Circuits and Systems
2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)
12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)
11th IEEE International Symposium on Asynchronous Circuits and Systems
10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings.
Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings.
Proceedings Eighth International Symposium on Asynchronous Circuits and Systems
Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001
Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001
Asynchronous design and the pursuit of low power
Exploiting typical DSP data access patterns and asynchrony for a low power multiported register bank
A low-power self-timed Viterbi decoder
A multi-radix approach to asynchronous division
A practical comparison of asynchronous design styles
GasP: a minimal FIFO control
PCA-1: a fully asynchronous, self-reconfigurable LSI
Efficient exact two-level hazard-free logic minimization
Partial-order correctness-preserving properties of delay-insensitive circuits
Synchronous handshake circuits
An analysis of reshuffled handshaking expansions
Designing an asynchronous bus interface
Delay insensitive system-on-chip interconnect using 1-of-4 data encoding
Synthesis and implementation of a signal-type asynchronous data communication mechanism
Where are the async millionaires?
An asynchronous superscalar architecture for exploiting instruction-level parallelism
AMULET3i cache architecture
Performance evaluation of Cascade ALU architecture for asynchronous super-scalar processors
FLEETzero: an asynchronous switching experiment
Designing fast asynchronous circuits
Squaring the FIFO in GasP
How to achieve worst-case performance [self-timed circuit design]
Testing asynchronous circuits: help is on the way!
Author index
Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems
Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems
Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems
Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems
Proceedings Second Working Conference on Asynchronous Design Methodologies
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems

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PCA-1: a fully asynchronous, self-reconfigurable LSI

Content Provider IEEE Xplore Digital Library
Author Konishi, R. Ito, H. Nakada, H. Nagoya, A. Oguri, K. Imlig, N. Shiozawa, T. Inamori, M. Nagami, K.
Copyright Year 2001
Description Author affiliation: NTT Network Innovation Labs., Kanagawa, Japan (Konishi, R.)
Abstract This paper describes the asynchronous device features of PCA-1, which is the first VLSI to realize the Plastic Cell Architecture (PCA). PCA is an autonomously reconfigurable hardware architecture consisting of a programmable logic layer and a network of built-in facilities. To realize run-time generation and the deletion of circuit objects with variable grain, the circuits on the logic layer are programmed as self-timed circuits using Look-Up Tables (LUTs). The built-in facilities of PCA-1 are also designed as self-timed circuits to enhance scalability and to minimize power consumption. LSI chips are successfully fabricated, and experimental results are mentioned.
Sponsorship IEEE Comput. Soc. Tech. Committee on VLSI
Starting Page 54
Ending Page 61
File Size 956673
Page Count 8
File Format PDF
ISBN 0769510345
ISSN 15228681
DOI 10.1109/ASYNC.2001.914069
Language English
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date 2001-03-11
Publisher Place USA
Access Restriction Subscribed
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword Large scale integration Circuits Principal component analysis Reconfigurable logic Very large scale integration Plastics Hardware Logic devices Programmable logic arrays Programmable logic devices
Content Type Text
Resource Type Article
Subject Engineering
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